sirlilpanda/esp32-racer
0
0
Fork 0
generated from sirlilpanda/kicad-project-template-actionless
Code Issues 6 Pull Requests Actions Packages Projects Releases Wiki Activity

Compare commits

base: sirlilpanda:d02ffe441746d2d87d79d1e8c8bb7a821b655e7e
Branches Tags
sirlilpanda:main sirlilpanda:PCB_ROUTING_ATTEMPT_1
...
compare: sirlilpanda:8d0db5fe0519324188cc2ee0285bee1e06854702
Branches Tags
sirlilpanda:main sirlilpanda:PCB_ROUTING_ATTEMPT_1

4 Commits
d02ffe4417 ... 8d0db5fe05

Author SHA1 Message Date
sirlilpanda
8d0db5fe05 auto commited 2026-04-14 22:31:58 +12:00
sirlilpanda
605dc84ea0 auto commited 2026-04-14 22:31:58 +12:00
sirlilpanda
937dc9bcec auto commited 2026-04-14 22:31:58 +12:00
sirlilpanda
cde648f312 WIP 2026-04-14 22:31:26 +12:00
4 changed files with 288 additions and 288 deletions
Expand all files Collapse all files

50
docs/esp32-racer_drc.rpt
View File

@@ -1,5 +1,5 @@
** Drc report for esp32-racer.kicad_pcb **
** Created on 2026-04-14T21:36:54 **
** Created on 2026-04-14T22:31:52 **
** Report includes: Errors, Warnings **
** Found 292 DRC violations **
@@ -175,6 +175,10 @@
Rule: board setup constraints courtyard; error
@(58.8000 mm, 116.3000 mm): Footprint R17
@(60.8850 mm, 117.7750 mm): Footprint C109
[clearance]: Clearance violation (zone clearance 0.5000 mm; actual 0.0000 mm)
Local override; error
@(145.8800 mm, 101.5550 mm): Track [/MCU/PWR_SWTICH_EN] on F.Cu, length 6.6550 mm
@(189.2500 mm, 52.0000 mm): Zone [GND] on F.Cu, B.Cu and 2 more, priority 0
[clearance]: Clearance violation (zone clearance 0.5000 mm; actual 0.0000 mm)
Local override; error
@(137.5750 mm, 101.5500 mm): Via [GND] on F.Cu - B.Cu
@@ -183,10 +187,6 @@
Rule: board setup constraints hole; error
@(137.5750 mm, 101.5500 mm): Via [GND] on F.Cu - B.Cu
@(110.0000 mm, 78.9000 mm): Zone [+3.3V] on In2.Cu, priority 11
[clearance]: Clearance violation (zone clearance 0.5000 mm; actual 0.0000 mm)
Local override; error
@(145.8800 mm, 101.5550 mm): Track [/MCU/PWR_SWTICH_EN] on F.Cu, length 6.6550 mm
@(189.2500 mm, 52.0000 mm): Zone [GND] on F.Cu, B.Cu and 2 more, priority 0
[clearance]: Clearance violation (zone clearance 0.5000 mm; actual 0.4369 mm)
Local override; error
@(149.3000 mm, 102.6000 mm): Track [Net-(U5-EN)] on F.Cu, length 1.4779 mm
@@ -203,6 +203,10 @@
Local override; error
@(202.7100 mm, 87.1000 mm): Pad 3 [GND] of Q18 on F.Cu
@(203.3500 mm, 87.1000 mm): Pad 4 [Net-(D34-A1)] of Q18 on F.Cu
[clearance]: Clearance violation ( clearance 0.2000 mm; actual 0.1400 mm)
Local override; error
@(122.1206 mm, 119.1295 mm): Pad 3 [+VPWR2] of Q13 on F.Cu
@(122.1206 mm, 119.7695 mm): Pad 4 [Net-(Q13-G)] of Q13 on F.Cu
[clearance]: Clearance violation ( clearance 0.2000 mm; actual 0.1400 mm)
Local override; error
@(127.8631 mm, 120.1795 mm): Pad 3 [Net-(M4--)] of Q14 on F.Cu
@@ -217,20 +221,24 @@
@(137.3131 mm, 117.7345 mm): Pad 4 [Net-(Q15-G)] of Q15 on F.Cu
[clearance]: Clearance violation ( clearance 0.2000 mm; actual 0.1400 mm)
Local override; error
@(122.1206 mm, 119.1295 mm): Pad 3 [+VPWR2] of Q13 on F.Cu
@(122.1206 mm, 119.7695 mm): Pad 4 [Net-(Q13-G)] of Q13 on F.Cu
@(132.2181 mm, 120.1795 mm): Pad 3 [Net-(M4-+)] of Q16 on F.Cu
@(132.8581 mm, 120.1795 mm): Pad 4 [Net-(Q16-G)] of Q16 on F.Cu
[clearance]: Clearance violation ( clearance 0.2000 mm; actual 0.1400 mm)
Local override; error
@(101.8524 mm, 119.1305 mm): Pad 3 [+VPWR2] of Q9 on F.Cu
@(101.8524 mm, 119.7705 mm): Pad 4 [Net-(Q9-G)] of Q9 on F.Cu
[clearance]: Clearance violation ( clearance 0.2000 mm; actual 0.1400 mm)
Local override; error
@(107.5949 mm, 120.1805 mm): Pad 3 [Net-(M3--)] of Q10 on F.Cu
@(108.2349 mm, 120.1805 mm): Pad 4 [Net-(Q10-G)] of Q10 on F.Cu
@(163.9040 mm, 119.2550 mm): Pad 3 [+VPWR1] of Q5 on F.Cu
@(163.9040 mm, 119.8950 mm): Pad 4 [Net-(Q5-G)] of Q5 on F.Cu
[clearance]: Clearance violation ( clearance 0.2000 mm; actual 0.1400 mm)
Local override; error
@(132.2181 mm, 120.1795 mm): Pad 3 [Net-(M4-+)] of Q16 on F.Cu
@(132.8581 mm, 120.1795 mm): Pad 4 [Net-(Q16-G)] of Q16 on F.Cu
@(117.0449 mm, 118.3755 mm): Pad 3 [+VPWR2] of Q11 on F.Cu
@(117.0449 mm, 117.7355 mm): Pad 4 [Net-(Q11-G)] of Q11 on F.Cu
[clearance]: Clearance violation ( clearance 0.2000 mm; actual 0.1400 mm)
Local override; error
@(107.5949 mm, 120.1805 mm): Pad 3 [Net-(M3--)] of Q10 on F.Cu
@(108.2349 mm, 120.1805 mm): Pad 4 [Net-(Q10-G)] of Q10 on F.Cu
[clearance]: Clearance violation (zone clearance 0.5000 mm; actual 0.0000 mm)
Local override; error
@(145.8800 mm, 101.5550 mm): Pad 1 [/MCU/PWR_SWTICH_EN] of R65 on F.Cu
@@ -239,18 +247,10 @@
Local override; error
@(147.5300 mm, 101.5550 mm): Pad 2 [Net-(U5-EN)] of R65 on F.Cu
@(189.2500 mm, 52.0000 mm): Zone [GND] on F.Cu, B.Cu and 2 more, priority 0
[clearance]: Clearance violation ( clearance 0.2000 mm; actual 0.1400 mm)
Local override; error
@(163.9040 mm, 119.2550 mm): Pad 3 [+VPWR1] of Q5 on F.Cu
@(163.9040 mm, 119.8950 mm): Pad 4 [Net-(Q5-G)] of Q5 on F.Cu
[clearance]: Clearance violation ( clearance 0.2000 mm; actual 0.1400 mm)
Local override; error
@(202.0475 mm, 80.0700 mm): Pad 3 [Net-(BT1--)] of Q17 on F.Cu
@(201.4075 mm, 80.0700 mm): Pad 4 [Net-(D32-A1)] of Q17 on F.Cu
[clearance]: Clearance violation ( clearance 0.2000 mm; actual 0.1400 mm)
Local override; error
@(117.0449 mm, 118.3755 mm): Pad 3 [+VPWR2] of Q11 on F.Cu
@(117.0449 mm, 117.7355 mm): Pad 4 [Net-(Q11-G)] of Q11 on F.Cu
[clearance]: Clearance violation ( clearance 0.2000 mm; actual 0.1400 mm)
Local override; error
@(174.0015 mm, 120.3050 mm): Pad 3 [Net-(M2-+)] of Q8 on F.Cu
@@ -963,12 +963,6 @@
[track_dangling]: Track has unconnected end
Local override; warning
@(55.0750 mm, 74.4000 mm): Track [Net-(J8-Pin_3)] on F.Cu, length 0.1250 mm
[track_dangling]: Track has unconnected end
Local override; warning
@(50.4000 mm, 85.6000 mm): Track [/MCU/PWR_SWTICH_EN] on F.Cu, length 0.1850 mm
[track_dangling]: Track has unconnected end
Local override; warning
@(139.2000 mm, 104.3000 mm): Track [/MCU/PWR_SWTICH_EN] on F.Cu, length 0.8100 mm
[track_dangling]: Track has unconnected end
Local override; warning
@(111.2787 mm, 102.4868 mm): Track [Net-(Q11-G)] on F.Cu, length 0.1149 mm
@@ -1005,6 +999,12 @@
[track_dangling]: Track has unconnected end
Local override; warning
@(75.6000 mm, 86.8000 mm): Track [/MCU/ENABLE_2] on F.Cu, length 0.2000 mm
[track_dangling]: Track has unconnected end
Local override; warning
@(50.4000 mm, 85.6000 mm): Track [/MCU/PWR_SWTICH_EN] on F.Cu, length 0.1850 mm
[track_dangling]: Track has unconnected end
Local override; warning
@(139.2000 mm, 104.3000 mm): Track [/MCU/PWR_SWTICH_EN] on F.Cu, length 0.8100 mm
[track_dangling]: Track has unconnected end
Local override; warning
@(108.7904 mm, 97.9527 mm): Track [/BOARD_STAT_MESUREMENT/MOTOR_DRIVER_3_I_SENSE] on F.Cu, length 0.1122 mm

6
docs/esp32-racer_erc.rpt
View File

@@ -1,4 +1,4 @@
ERC report (2026-04-14T21:36:56, Encoding UTF8)
ERC report (2026-04-14T22:31:54, Encoding UTF8)
Report includes: Errors, Warnings
***** Sheet /
@@ -174,8 +174,8 @@ Report includes: Errors, Warnings
@(236.22 mm, 22.86 mm): Label '5v@2.5A'
[multiple_net_names]: Both +8V and 8v@3A are attached to the same items; +8V will be used in the netlist
; warning
@(173.99 mm, 123.19 mm): Symbol #PWR089 Pin 1 [Power input, Line]
@(273.05 mm, 85.09 mm): Label '8v@3A'
@(280.67 mm, 74.93 mm): Symbol #PWR0114 Pin 1 [Power input, Line]
@(240.03 mm, 85.09 mm): Label '8v@3A'
[multiple_net_names]: Both +3.3V and 3.3v@1A are attached to the same items; +3.3V will be used in the netlist
; warning
@(276.86 mm, 146.05 mm): Symbol #PWR0110 Pin 1 [Power input, Line]

BIN
docs/esp32-racer_schematic.pdf
View File

Binary file not shown.

520
hardware/esp32-racer/esp32-racer.kicad_pcb
View File

@@ -123758,232 +123758,68 @@
(uuid "fd0d36f4-7b14-490e-8a10-d80bf7b11919")
)
(segment
(start 50.42 84.365)
(end 50.4 84.385)
(start 152.819487 109.924563)
(end 152.819487 110.656)
(width 0.2)
(layer "F.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "177ebdc8-a29a-46eb-9c19-56e9276e83ab")
(net "Net-(U5-EN)")
(uuid "2aaf31ba-7873-41be-94d1-b1b47b6c62f7")
)
(segment
(start 140.315 108.844425)
(end 139.2 107.729425)
(start 149.3 107)
(end 149.3 102.6)
(width 0.2)
(layer "F.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "2f03de77-0f74-4f35-9190-fe259ecd2dd6")
(net "Net-(U5-EN)")
(uuid "394bbb30-90af-4245-a3d0-7f8ba9698cf5")
)
(segment
(start 50.4 85.6)
(end 50.4 85.415)
(start 149.3 102.6)
(end 148.255 101.555)
(width 0.2)
(layer "F.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "2f1f73dc-bf91-4557-b58b-ef8604883bbd")
(net "Net-(U5-EN)")
(uuid "3ffb6cb2-56d9-4d3e-8ce4-d2d4440765f1")
)
(segment
(start 145.88 101.555)
(end 139.225 101.555)
(start 152.819487 110.656)
(end 152.988487 110.825)
(width 0.2)
(layer "F.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "486b2a18-e742-4b18-a774-e9977d745084")
(net "Net-(U5-EN)")
(uuid "9604cc07-b558-41c1-9b1b-0d638194efef")
)
(segment
(start 139.2 104.3)
(end 139.2 96.05)
(start 151.689349 108.794425)
(end 151.094425 108.794425)
(width 0.2)
(layer "F.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "4a977ae0-db4e-4011-9460-f98ef876dd38")
(net "Net-(U5-EN)")
(uuid "b3728c0f-4587-4ee1-ac74-cb37989ec003")
)
(segment
(start 141.679576 110.209001)
(end 140.315 108.844425)
(start 148.255 101.555)
(end 147.53 101.555)
(width 0.2)
(layer "F.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "4efd20e4-77d0-4d4c-b30f-1d5120ac8b80")
(net "Net-(U5-EN)")
(uuid "ba2b9fa8-3827-45a9-a5d1-bbe165f27299")
)
(segment
(start 60.5 87.2)
(end 52 87.2)
(start 151.094425 108.794425)
(end 149.3 107)
(width 0.2)
(layer "F.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "5f44fdd2-065e-47ba-a536-40b5dcdba699")
(net "Net-(U5-EN)")
(uuid "ba97dd47-b154-40fe-9551-5cd19588d562")
)
(segment
(start 142.281501 110.209001)
(end 141.679576 110.209001)
(start 151.689349 108.794425)
(end 152.819487 109.924563)
(width 0.2)
(layer "F.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "664e25c5-38cc-4600-9dcc-bcc8f56a5076")
)
(segment
(start 139.2 96.05)
(end 138.6 95.45)
(width 0.2)
(layer "F.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "7b653cb1-df4c-40e6-9a6b-c0591851c05a")
)
(segment
(start 139.2 104.3)
(end 139.2 103.49)
(width 0.2)
(layer "F.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "909a6900-36f3-46bb-b980-0369d232cb4c")
)
(segment
(start 137.15 95.45)
(end 138.6 95.45)
(width 0.2)
(layer "F.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "a2062619-1fa8-4273-a943-4fde14c07a54")
)
(segment
(start 142.3825 110.825)
(end 142.3825 110.31)
(width 0.2)
(layer "F.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "a585f6eb-e5e6-4e36-9916-cb95c6733267")
)
(segment
(start 142.3825 110.31)
(end 142.281501 110.209001)
(width 0.2)
(layer "F.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "c9357241-b387-4476-b5f6-7c825442c7fe")
)
(segment
(start 52 87.2)
(end 50.4 85.6)
(width 0.2)
(layer "F.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "d25e52e4-bcfc-4b0a-8414-80a110a6566d")
)
(segment
(start 139.2 107.729425)
(end 139.2 104.3)
(width 0.2)
(layer "F.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "e05973c8-7797-4825-97f4-ec323d2c8d47")
)
(segment
(start 50.4 84.385)
(end 50.4 85.6)
(width 0.2)
(layer "F.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "f62ae2cd-d78a-45c0-b839-635292c61d4a")
)
(via
(at 60.5 87.2)
(size 0.6)
(drill 0.3)
(layers "F.Cu" "B.Cu")
(capping no)
(covering
(front no)
(back no)
)
(plugging
(front no)
(back no)
)
(filling no)
(net "/MCU/PWR_SWTICH_EN")
(uuid "37b9fd74-3ee9-4cd0-9581-4dbd89991853")
)
(via
(at 137.15 95.45)
(size 0.6)
(drill 0.3)
(layers "F.Cu" "B.Cu")
(capping no)
(covering
(front no)
(back no)
)
(plugging
(front no)
(back no)
)
(filling no)
(net "/MCU/PWR_SWTICH_EN")
(uuid "ca1ffd20-6082-4b20-aa2b-9aff3b08735b")
)
(segment
(start 78 87.2)
(end 60.5 87.2)
(width 0.2)
(layer "B.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "0be3ab6a-ed49-43b8-9fc1-fcd0b2bea8f9")
)
(segment
(start 135.3 93.6)
(end 108 93.6)
(width 0.2)
(layer "B.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "663f0e35-9a18-4eb9-b26f-9f2b12a351ed")
)
(segment
(start 102.3 95.8)
(end 96.4 101.7)
(width 0.2)
(layer "B.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "69a286e1-588d-4f40-8ec4-1d5877951d45")
)
(segment
(start 96.4 101.7)
(end 92.5 101.7)
(width 0.2)
(layer "B.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "7e767601-213f-492a-9e84-11a1f7013a08")
)
(segment
(start 92.5 101.7)
(end 78 87.2)
(width 0.2)
(layer "B.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "85ca4378-60a1-4e1f-9ad4-0c846c22f8b4")
)
(segment
(start 137.15 95.45)
(end 135.3 93.6)
(width 0.2)
(layer "B.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "9c4c2e56-67a7-4394-b376-6d01c92c3834")
)
(segment
(start 105.8 95.8)
(end 102.3 95.8)
(width 0.2)
(layer "B.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "9f852b6d-05dd-4512-9129-e8dda4bbe4e6")
)
(segment
(start 108 93.6)
(end 105.8 95.8)
(width 0.2)
(layer "B.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "de5faf33-f5db-4557-addc-8a9a69b693cd")
(net "Net-(U5-EN)")
(uuid "f6c50595-4644-47b3-a71a-e30c18a66388")
)
(segment
(start 194.500609 99.288075)
@@ -130066,6 +129902,234 @@
(net "Net-(U4-VCC)")
(uuid "eba0b7c0-2ba7-468f-bda4-5fe85b10d439")
)
(segment
(start 50.42 84.365)
(end 50.4 84.385)
(width 0.2)
(layer "F.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "177ebdc8-a29a-46eb-9c19-56e9276e83ab")
)
(segment
(start 140.315 108.844425)
(end 139.2 107.729425)
(width 0.2)
(layer "F.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "2f03de77-0f74-4f35-9190-fe259ecd2dd6")
)
(segment
(start 50.4 85.6)
(end 50.4 85.415)
(width 0.2)
(layer "F.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "2f1f73dc-bf91-4557-b58b-ef8604883bbd")
)
(segment
(start 145.88 101.555)
(end 139.225 101.555)
(width 0.2)
(layer "F.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "486b2a18-e742-4b18-a774-e9977d745084")
)
(segment
(start 139.2 104.3)
(end 139.2 96.05)
(width 0.2)
(layer "F.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "4a977ae0-db4e-4011-9460-f98ef876dd38")
)
(segment
(start 141.679576 110.209001)
(end 140.315 108.844425)
(width 0.2)
(layer "F.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "4efd20e4-77d0-4d4c-b30f-1d5120ac8b80")
)
(segment
(start 60.5 87.2)
(end 52 87.2)
(width 0.2)
(layer "F.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "5f44fdd2-065e-47ba-a536-40b5dcdba699")
)
(segment
(start 142.281501 110.209001)
(end 141.679576 110.209001)
(width 0.2)
(layer "F.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "664e25c5-38cc-4600-9dcc-bcc8f56a5076")
)
(segment
(start 139.2 96.05)
(end 138.6 95.45)
(width 0.2)
(layer "F.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "7b653cb1-df4c-40e6-9a6b-c0591851c05a")
)
(segment
(start 139.2 104.3)
(end 139.2 103.49)
(width 0.2)
(layer "F.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "909a6900-36f3-46bb-b980-0369d232cb4c")
)
(segment
(start 137.15 95.45)
(end 138.6 95.45)
(width 0.2)
(layer "F.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "a2062619-1fa8-4273-a943-4fde14c07a54")
)
(segment
(start 142.3825 110.825)
(end 142.3825 110.31)
(width 0.2)
(layer "F.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "a585f6eb-e5e6-4e36-9916-cb95c6733267")
)
(segment
(start 142.3825 110.31)
(end 142.281501 110.209001)
(width 0.2)
(layer "F.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "c9357241-b387-4476-b5f6-7c825442c7fe")
)
(segment
(start 52 87.2)
(end 50.4 85.6)
(width 0.2)
(layer "F.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "d25e52e4-bcfc-4b0a-8414-80a110a6566d")
)
(segment
(start 139.2 107.729425)
(end 139.2 104.3)
(width 0.2)
(layer "F.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "e05973c8-7797-4825-97f4-ec323d2c8d47")
)
(segment
(start 50.4 84.385)
(end 50.4 85.6)
(width 0.2)
(layer "F.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "f62ae2cd-d78a-45c0-b839-635292c61d4a")
)
(via
(at 60.5 87.2)
(size 0.6)
(drill 0.3)
(layers "F.Cu" "B.Cu")
(capping no)
(covering
(front no)
(back no)
)
(plugging
(front no)
(back no)
)
(filling no)
(net "/MCU/PWR_SWTICH_EN")
(uuid "37b9fd74-3ee9-4cd0-9581-4dbd89991853")
)
(via
(at 137.15 95.45)
(size 0.6)
(drill 0.3)
(layers "F.Cu" "B.Cu")
(capping no)
(covering
(front no)
(back no)
)
(plugging
(front no)
(back no)
)
(filling no)
(net "/MCU/PWR_SWTICH_EN")
(uuid "ca1ffd20-6082-4b20-aa2b-9aff3b08735b")
)
(segment
(start 78 87.2)
(end 60.5 87.2)
(width 0.2)
(layer "B.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "0be3ab6a-ed49-43b8-9fc1-fcd0b2bea8f9")
)
(segment
(start 135.3 93.6)
(end 108 93.6)
(width 0.2)
(layer "B.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "663f0e35-9a18-4eb9-b26f-9f2b12a351ed")
)
(segment
(start 102.3 95.8)
(end 96.4 101.7)
(width 0.2)
(layer "B.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "69a286e1-588d-4f40-8ec4-1d5877951d45")
)
(segment
(start 96.4 101.7)
(end 92.5 101.7)
(width 0.2)
(layer "B.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "7e767601-213f-492a-9e84-11a1f7013a08")
)
(segment
(start 92.5 101.7)
(end 78 87.2)
(width 0.2)
(layer "B.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "85ca4378-60a1-4e1f-9ad4-0c846c22f8b4")
)
(segment
(start 137.15 95.45)
(end 135.3 93.6)
(width 0.2)
(layer "B.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "9c4c2e56-67a7-4394-b376-6d01c92c3834")
)
(segment
(start 105.8 95.8)
(end 102.3 95.8)
(width 0.2)
(layer "B.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "9f852b6d-05dd-4512-9129-e8dda4bbe4e6")
)
(segment
(start 108 93.6)
(end 105.8 95.8)
(width 0.2)
(layer "B.Cu")
(net "/MCU/PWR_SWTICH_EN")
(uuid "de5faf33-f5db-4557-addc-8a9a69b693cd")
)
(via
(at 197 74.3)
(size 0.6)
@@ -139716,70 +139780,6 @@
(net "/MCU/PROG_UART_TX")
(uuid "c04b7a44-8b42-43f7-bc82-bfecf4b00ddc")
)
(segment
(start 152.819487 109.924563)
(end 152.819487 110.656)
(width 0.2)
(layer "F.Cu")
(net "Net-(U5-EN)")
(uuid "2aaf31ba-7873-41be-94d1-b1b47b6c62f7")
)
(segment
(start 149.3 107)
(end 149.3 102.6)
(width 0.2)
(layer "F.Cu")
(net "Net-(U5-EN)")
(uuid "394bbb30-90af-4245-a3d0-7f8ba9698cf5")
)
(segment
(start 149.3 102.6)
(end 148.255 101.555)
(width 0.2)
(layer "F.Cu")
(net "Net-(U5-EN)")
(uuid "3ffb6cb2-56d9-4d3e-8ce4-d2d4440765f1")
)
(segment
(start 152.819487 110.656)
(end 152.988487 110.825)
(width 0.2)
(layer "F.Cu")
(net "Net-(U5-EN)")
(uuid "9604cc07-b558-41c1-9b1b-0d638194efef")
)
(segment
(start 151.689349 108.794425)
(end 151.094425 108.794425)
(width 0.2)
(layer "F.Cu")
(net "Net-(U5-EN)")
(uuid "b3728c0f-4587-4ee1-ac74-cb37989ec003")
)
(segment
(start 148.255 101.555)
(end 147.53 101.555)
(width 0.2)
(layer "F.Cu")
(net "Net-(U5-EN)")
(uuid "ba2b9fa8-3827-45a9-a5d1-bbe165f27299")
)
(segment
(start 151.094425 108.794425)
(end 149.3 107)
(width 0.2)
(layer "F.Cu")
(net "Net-(U5-EN)")
(uuid "ba97dd47-b154-40fe-9551-5cd19588d562")
)
(segment
(start 151.689349 108.794425)
(end 152.819487 109.924563)
(width 0.2)
(layer "F.Cu")
(net "Net-(U5-EN)")
(uuid "f6c50595-4644-47b3-a71a-e30c18a66388")
)
(zone
(net "Net-(Q6-S)")
(layer "F.Cu")