auto commited

docs/test_drc.rpt

@@ -1,6 +1,5 @@
 ** Drc report for test.kicad_pcb **
-** Created on 2026-05-20T17:59:02 **
+** Created on 2026-05-21T19:14:19+1200 **
-** Report includes: Errors, Warnings **
 
 ** Found 1 DRC violations **
 [invalid_outline]: Board has malformed outline (no edges found on Edge.Cuts layer)
@@ -11,11 +10,4 @@
 
 ** Found 0 Footprint errors **
 
-** Ignored checks **
-    - Footprint has no courtyard defined
-    - Track endpoint not centered on via
-    - Tuning profile track geometries
-    - Footprint doesn't match symbol's footprint filters
-    - Footprint component type doesn't match footprint pads
-
 ** End of Report **

docs/test_erc.rpt

@@ -1,12 +1,5 @@
-ERC report (2026-05-20T17:59:04, Encoding UTF8)
+ERC report (2026-05-21T19:14:19+1200, Encoding UTF8)
-Report includes: Errors, Warnings
 
 ***** Sheet /
 
  ** ERC messages: 0  Errors 0  Warnings 0
-
- ** Ignored checks:
-    - Global label only appears once in the schematic
-    - Four connection points are joined together
-    - SPICE model issue
-    - Assigned footprint doesn't match footprint filters

hardware/holder/holder.kicad_prl

@@ -1,10 +1,12 @@
 {
   "board": {
-    "active_layer": 0,
+    "active_layer": 41,
     "active_layer_preset": "",
     "auto_track_width": true,
     "hidden_netclasses": [],
-    "hidden_nets": [],
+    "hidden_nets": [
+      "GND"
+    ],
     "high_contrast_mode": 0,
     "net_color_mode": 1,
     "opacity": {
@@ -17,17 +19,17 @@
     },
     "prototype_zone_fills": false,
     "selection_filter": {
-      "dimensions": true,
+      "dimensions": false,
-      "footprints": true,
+      "footprints": false,
-      "graphics": true,
+      "graphics": false,
-      "keepouts": true,
+      "keepouts": false,
       "lockedItems": false,
-      "otherItems": true,
+      "otherItems": false,
-      "pads": true,
+      "pads": false,
-      "text": true,
+      "text": false,
-      "tracks": true,
+      "tracks": false,
       "vias": true,
-      "zones": true
+      "zones": false
     },
     "visible_items": [
       "vias",
@@ -53,7 +55,7 @@
       "board_outline_area",
       "ly_points"
     ],
-    "visible_layers": "ffffffff_ffffffff_fffffff5_ffffffff",
+    "visible_layers": "ffffffff_ffffffff_fffffffd_ffffffff",
     "zone_display_mode": 0
   },
   "git": {
@@ -77,6 +79,8 @@
       false,
       false,
       false,
+      false,
+      false,
       false
     ],
     "col_order": [
@@ -89,7 +93,9 @@
       6,
       7,
       8,
-      9
+      9,
+      10,
+      11
     ],
     "col_widths": [],
     "custom_group_rules": [],

hardware/holder/holder.kicad_pro

@@ -522,7 +522,7 @@
     "last_paths": {
       "idf": "",
       "netlist": "",
-      "plot": "",
+      "plot": "../../PCBs/REV_A/",
       "specctra_dsn": "",
       "vrml": ""
     },
@@ -658,7 +658,7 @@
         "uuid": "8275422a-036f-4c2a-bd68-eba183244099"
       }
     ],
-    "used_designators": "TP1-24,J1-13,#PWR1-48,L1-12,C1-24,U1",
+    "used_designators": "",
     "variants": []
   },
   "sheets": [