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panda
2026-07-17 11:18:57 +12:00
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.gitignore vendored Normal file
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.zig-cache/
zig-out/

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STM32G431CBTx_FLASH.ld Normal file
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/*
******************************************************************************
**
** File : LinkerScript.ld
**
** Author : STM32CubeMX
**
** Abstract : Linker script for STM32G431CBTx series
** 112Kbytes FLASH and 32Kbytes RAM
**
** Set heap size, stack size and stack location according
** to application requirements.
**
** Set memory bank area and size if external memory is used.
**
** Target : STMicroelectronics STM32
**
** Distribution: The file is distributed “as is,” without any warranty
** of any kind.
**
*****************************************************************************
** @attention
**
** <h2><center>&copy; COPYRIGHT(c) 2019 STMicroelectronics</center></h2>
**
** Redistribution and use in source and binary forms, with or without modification,
** are permitted provided that the following conditions are met:
** 1. Redistributions of source code must retain the above copyright notice,
** this list of conditions and the following disclaimer.
** 2. Redistributions in binary form must reproduce the above copyright notice,
** this list of conditions and the following disclaimer in the documentation
** and/or other materials provided with the distribution.
** 3. Neither the name of STMicroelectronics nor the names of its contributors
** may be used to endorse or promote products derived from this software
** without specific prior written permission.
**
** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
** AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
** IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
** FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
** DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
** SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
** CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
** OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
** OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**
*****************************************************************************
*/
/* Entry Point */
ENTRY(Reset_Handler)
/* Generate a link error if heap and stack don't fit into RAM */
_Min_Heap_Size = 0x200; /* required amount of heap */
_Min_Stack_Size = 0x400; /* required amount of stack */
/* Specify the memory areas */
MEMORY
{
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K
FLASH (rx) : ORIGIN = 0x8000000, LENGTH = 112K
}
/* _estack = ORIGIN(RAM) + LENGTH(RAM); */
_estack = 0x20008000;
/* Highest address of the user mode stack */
/* Define output sections */
SECTIONS
{
/* The startup code goes first into FLASH */
.isr_vector :
{
. = ALIGN(4);
KEEP(*(.isr_vector)) /* Startup code */
. = ALIGN(4);
} >FLASH
/* The program code and other data goes into FLASH */
.text :
{
. = ALIGN(4);
*(.text) /* .text sections (code) */
*(.text*) /* .text* sections (code) */
*(.glue_7) /* glue arm to thumb code */
*(.glue_7t) /* glue thumb to arm code */
*(.eh_frame)
KEEP (*(.init))
KEEP (*(.fini))
. = ALIGN(4);
_etext = .; /* define a global symbols at end of code */
} >FLASH
/* Constant data goes into FLASH */
.rodata :
{
. = ALIGN(4);
*(.rodata) /* .rodata sections (constants, strings, etc.) */
*(.rodata*) /* .rodata* sections (constants, strings, etc.) */
. = ALIGN(4);
} >FLASH
/* used by the startup to initialize data */
_sidata = LOADADDR(.data);
/* Initialized data sections goes into RAM, load LMA copy after code */
.data :
{
. = ALIGN(4);
_sdata = .; /* create a global symbol at data start */
*(.data) /* .data sections */
*(.data*) /* .data* sections */
. = ALIGN(4);
_edata = .; /* define a global symbol at data end */
} >RAM AT> FLASH
/* Uninitialized data section */
. = ALIGN(4);
.bss :
{
/* This is used by the startup in order to initialize the .bss secion */
_sbss = .; /* define a global symbol at bss start */
__bss_start__ = _sbss;
*(.bss)
*(.bss*)
*(COMMON)
. = ALIGN(4);
_ebss = .; /* define a global symbol at bss end */
__bss_end__ = _ebss;
} >RAM
/* User_heap_stack section, used to check that there is enough RAM left */
._user_heap_stack :
{
. = ALIGN(8);
PROVIDE ( end = . );
PROVIDE ( _end = . );
. = . + _Min_Heap_Size;
. = . + _Min_Stack_Size;
. = ALIGN(8);
} >RAM
/* Remove information from the standard libraries */
/DISCARD/ :
{
libc.a ( * )
libm.a ( * )
libgcc.a ( * )
}
.ARM.attributes 0 : { *(.ARM.attributes) }
}

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const std = @import("std");
pub fn build(b: *std.Build) void {
const optimize = b.standardOptimizeOption(.{
.preferred_optimize_mode = .ReleaseSmall,
});
const target = b.resolveTargetQuery(.{
.cpu_arch = .thumb,
.cpu_model = .{
.explicit = &std.Target.arm.cpu.cortex_m4,
},
.os_tag = .freestanding,
.abi = .eabihf,
});
// const mod = b.addModule("zig_stm32g4_test", .{
// .root_source_file = b.path("src/root.zig"),
// .target = target,
// });
const exe = b.addExecutable(.{
.name = "zig_stm32g4_test",
.root_module = b.createModule(.{
.root_source_file = b.path("src/main.zig"),
.target = target,
.optimize = optimize,
}),
});
exe.dead_strip_dylibs = true;
exe.link_gc_sections = true;
exe.link_function_sections = true;
exe.link_data_sections = true;
exe.lto = .full;
exe.discard_local_symbols = true;
const bin = exe.addObjCopy(.{ .format = .bin });
const install_exe = b.addInstallArtifact(exe, .{});
const install_bin = b.addInstallBinFile(bin.getOutput(), bin.basename);
exe.setLinkerScript(b.path("stm32g431cbtx.ld"));
b.getInstallStep().dependOn(&install_bin.step);
install_bin.step.dependOn(&install_exe.step);
b.installArtifact(exe);
// const run_step = b.step("run", "Run the app");
// const run_cmd = b.addRunArtifact(exe);
// run_step.dependOn(&run_cmd.step);
// run_cmd.step.dependOn(b.getInstallStep());
// if (b.args) |args| {
// run_cmd.addArgs(args);
// }
// const mod_tests = b.addTest(.{
// .root_module = mod,
// });
// const run_mod_tests = b.addRunArtifact(mod_tests);
// const exe_tests = b.addTest(.{
// .root_module = exe.root_module,
// });
// const run_exe_tests = b.addRunArtifact(exe_tests);
// const test_step = b.step("test", "Run tests");
// test_step.dependOn(&run_mod_tests.step);
// test_step.dependOn(&run_exe_tests.step);
}

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.{
// This is the default name used by packages depending on this one. For
// example, when a user runs `zig fetch --save <url>`, this field is used
// as the key in the `dependencies` table. Although the user can choose a
// different name, most users will stick with this provided value.
//
// It is redundant to include "zig" in this name because it is already
// within the Zig package namespace.
.name = .zig_stm32g4_test,
// This is a [Semantic Version](https://semver.org/).
// In a future version of Zig it will be used for package deduplication.
.version = "0.0.0",
// Together with name, this represents a globally unique package
// identifier. This field is generated by the Zig toolchain when the
// package is first created, and then *never changes*. This allows
// unambiguous detection of one package being an updated version of
// another.
//
// When forking a Zig project, this id should be regenerated (delete the
// field and run `zig build`) if the upstream project is still maintained.
// Otherwise, the fork is *hostile*, attempting to take control over the
// original project's identity. Thus it is recommended to leave the comment
// on the following line intact, so that it shows up in code reviews that
// modify the field.
.fingerprint = 0x4f284c3907fb64c0, // Changing this has security and trust implications.
// Tracks the earliest Zig version that the package considers to be a
// supported use case.
.minimum_zig_version = "0.16.0",
// This field is optional.
// Each dependency must either provide a `url` and `hash`, or a `path`.
// `zig build --fetch` can be used to fetch all dependencies of a package, recursively.
// Once all dependencies are fetched, `zig build` no longer requires
// internet connectivity.
.dependencies = .{
// See `zig fetch --save <url>` for a command-line interface for adding dependencies.
//.example = .{
// // When updating this field to a new URL, be sure to delete the corresponding
// // `hash`, otherwise you are communicating that you expect to find the old hash at
// // the new URL. If the contents of a URL change this will result in a hash mismatch
// // which will prevent zig from using it.
// .url = "https://example.com/foo.tar.gz",
//
// // This is computed from the file contents of the directory of files that is
// // obtained after fetching `url` and applying the inclusion rules given by
// // `paths`.
// //
// // This field is the source of truth; packages do not come from a `url`; they
// // come from a `hash`. `url` is just one of many possible mirrors for how to
// // obtain a package matching this `hash`.
// //
// // Uses the [multihash](https://multiformats.io/multihash/) format.
// .hash = "...",
//
// // When this is provided, the package is found in a directory relative to the
// // build root. In this case the package's hash is irrelevant and therefore not
// // computed. This field and `url` are mutually exclusive.
// .path = "foo",
//
// // When this is set to `true`, a package is declared to be lazily
// // fetched. This makes the dependency only get fetched if it is
// // actually used.
// .lazy = false,
//},
},
// Specifies the set of files and directories that are included in this package.
// Only files and directories listed here are included in the `hash` that
// is computed for this package. Only files listed here will remain on disk
// when using the zig package manager. As a rule of thumb, one should list
// files required for compilation plus any license(s).
// Paths are relative to the build root. Use the empty string (`""`) to refer to
// the build root itself.
// A directory listed here means that all files within, recursively, are included.
.paths = .{
"build.zig",
"build.zig.zon",
"src",
// For example...
//"LICENSE",
//"README.md",
},
}

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const std = @import("std");
const Io = std.Io;
export fn resetHandler() callconv(.c) void {
_start();
}
export fn _start() void {
// const io = std.Io{
// .vtable
// };
try main(undefined);
while (true) {
asm volatile ("nop");
}
}
pub fn main(init: std.process.Init) !void {
_ = init;
asm volatile ("nop");
}
export fn nmiHandler() callconv(.c) void {}
export fn hardFaultHandler() callconv(.c) void {}
export fn memManageHandler() callconv(.c) void {}
export fn busFaultHandler() callconv(.c) void {}
export fn usageFaultHandler() callconv(.c) void {}
export fn svCallHandler() callconv(.c) void {}
export fn debugMonitorHandler() callconv(.c) void {}
export fn pendSvHandler() callconv(.c) void {}
export fn sysTickHandler() callconv(.c) void {}
export const vectors linksection(".vectors") = [_]?*const fn () callconv(.c) void{
resetHandler,
nmiHandler,
hardFaultHandler,
memManageHandler,
busFaultHandler,
usageFaultHandler,
null, // reserved
null, // reserved
null, // reserved
null, // reserved
svCallHandler,
debugMonitorHandler,
null, // reserved
pendSvHandler,
sysTickHandler,
// -- snip: continued for MCU-specific interrupts; consult datasheet
};

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// //! By convention, root.zig is the root source file when making a package.
// const std = @import("std");
// const Io = std.Io;
// /// This is a documentation comment to explain the `printAnotherMessage` function below.
// ///
// /// Accepting an `Io.Writer` instance is a handy way to write reusable code.
// pub fn printAnotherMessage(writer: *Io.Writer) Io.Writer.Error!void {
// try writer.print("Run `zig build test` to run the tests.\n", .{});
// }
// pub fn add(a: i32, b: i32) i32 {
// return a + b;
// }
// test "basic add functionality" {
// try std.testing.expect(add(3, 7) == 10);
// }

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//! Description for STM32G431
const microzig = @import("microzig");
const mmio = microzig.mmio;
pub const types = @import("types.zig");
pub const Properties = struct {
has_vtor: ?bool = null,
has_mpu: ?bool = null,
has_fpu: ?bool = null,
interrupt_priority_bits: ?u8 = null,
dma_channel_count: ?u32 = null,
};
pub const Interrupt = struct {
name: [:0]const u8,
index: i16,
description: ?[:0]const u8,
};
pub const properties: Properties = .{
.has_vtor = null,
.has_mpu = true,
.has_fpu = true,
.interrupt_priority_bits = 4,
.dma_channel_count = null,
};
pub const raw_properties = struct {
pub const @"cpu.endian" = "little";
pub const @"cpu.fpuPresent" = "true";
pub const @"cpu.mpuPresent" = "true";
pub const @"cpu.name" = "CM4";
pub const @"cpu.nvicPrioBits" = "4";
pub const @"cpu.revision" = "r0p1";
pub const @"cpu.vendorSystickConfig" = "false";
};
pub const interrupts: []const Interrupt = &.{
.{ .name = "NMI", .index = -14, .description = null },
.{ .name = "HardFault", .index = -13, .description = null },
.{ .name = "MemManageFault", .index = -12, .description = null },
.{ .name = "BusFault", .index = -11, .description = null },
.{ .name = "UsageFault", .index = -10, .description = null },
.{ .name = "SVCall", .index = -5, .description = null },
.{ .name = "PendSV", .index = -2, .description = null },
.{ .name = "SysTick", .index = -1, .description = null },
.{ .name = "WWDG", .index = 0, .description = "Window Watchdog interrupt" },
.{ .name = "PVD_PVM", .index = 1, .description = "PVD through EXTI line detection" },
.{ .name = "RTC_TAMP_CSS_LSE", .index = 2, .description = "RTC_TAMP_CSS_LSE" },
.{ .name = "RTC_WKUP", .index = 3, .description = "RTC Wakeup timer" },
.{ .name = "FLASH", .index = 4, .description = "FLASH" },
.{ .name = "RCC", .index = 5, .description = "RCC global interrupt" },
.{ .name = "EXTI0", .index = 6, .description = "EXTI Line0 interrupt" },
.{ .name = "EXTI1", .index = 7, .description = "EXTI Line1 interrupt" },
.{ .name = "EXTI2", .index = 8, .description = "EXTI Line2 interrupt" },
.{ .name = "EXTI3", .index = 9, .description = "EXTI Line3 interrupt" },
.{ .name = "EXTI4", .index = 10, .description = "EXTI Line4 interrupt" },
.{ .name = "DMA1_CH1", .index = 11, .description = "DMA1 channel 1 interrupt" },
.{ .name = "DMA1_CH2", .index = 12, .description = "DMA1 channel 2 interrupt" },
.{ .name = "DMA1_CH3", .index = 13, .description = "DMA1 channel 3 interrupt" },
.{ .name = "DMA1_CH4", .index = 14, .description = "DMA1 channel 4 interrupt" },
.{ .name = "DMA1_CH5", .index = 15, .description = "DMA1 channel 5 interrupt" },
.{ .name = "DMA1_CH6", .index = 16, .description = "DMA1 channel 6 interrupt" },
.{ .name = "ADC1_2", .index = 18, .description = "ADC1 and ADC2 global interrupt" },
.{ .name = "USB_HP", .index = 19, .description = "USB_HP" },
.{ .name = "USB_LP", .index = 20, .description = "USB_LP" },
.{ .name = "FDCAN1_IT0", .index = 21, .description = "FDCAN1 interrupt 0" },
.{ .name = "FDCAN1_IT1", .index = 22, .description = "FDCAN1 interrupt 1" },
.{ .name = "EXTI9_5", .index = 23, .description = "EXTI9_5" },
.{ .name = "TIM1_BRK_TIM15", .index = 24, .description = "TIM1_BRK_TIM15" },
.{ .name = "TIM1_UP_TIM16", .index = 25, .description = "TIM1_UP_TIM16" },
.{ .name = "TIM1_TRG_COM", .index = 26, .description = "TIM1_TRG_COM/" },
.{ .name = "TIM1_CC", .index = 27, .description = "TIM1 capture compare interrupt" },
.{ .name = "TIM2", .index = 28, .description = "TIM2" },
.{ .name = "TIM3", .index = 29, .description = "TIM3" },
.{ .name = "TIM4", .index = 30, .description = "TIM4" },
.{ .name = "I2C1_EV", .index = 31, .description = "I2C1_EV" },
.{ .name = "I2C1_ER", .index = 32, .description = "I2C1_ER" },
.{ .name = "I2C2_EV", .index = 33, .description = "I2C2_EV" },
.{ .name = "I2C2_ER", .index = 34, .description = "I2C2_ER" },
.{ .name = "SPI1", .index = 35, .description = "SPI1" },
.{ .name = "SPI2", .index = 36, .description = "SPI2" },
.{ .name = "USART1", .index = 37, .description = "USART1" },
.{ .name = "USART2", .index = 38, .description = "USART2" },
.{ .name = "USART3", .index = 39, .description = "USART3" },
.{ .name = "EXTI15_10", .index = 40, .description = "EXTI15_10" },
.{ .name = "RTC_ALARM", .index = 41, .description = "RTC_ALARM" },
.{ .name = "USBWakeUP", .index = 42, .description = "USBWakeUP" },
.{ .name = "TIM8_BRK", .index = 43, .description = "TIM8_BRK" },
.{ .name = "TIM8_UP", .index = 44, .description = "TIM8_UP" },
.{ .name = "TIM8_TRG_COM", .index = 45, .description = "TIM8_TRG_COM" },
.{ .name = "TIM8_CC", .index = 46, .description = "TIM8_CC" },
.{ .name = "LPTIM1", .index = 49, .description = "LPTIM1" },
.{ .name = "SPI3", .index = 51, .description = "SPI3" },
.{ .name = "UART4", .index = 52, .description = "UART4" },
.{ .name = "TIM6_DACUNDER", .index = 54, .description = "TIM6_DACUNDER" },
.{ .name = "TIM7", .index = 55, .description = "TIM7" },
.{ .name = "DMA2_CH1", .index = 56, .description = "DMA2_CH1" },
.{ .name = "DMA2_CH2", .index = 57, .description = "DMA2_CH2" },
.{ .name = "DMA2_CH3", .index = 58, .description = "DMA2_CH3" },
.{ .name = "DMA2_CH4", .index = 59, .description = "DMA2_CH4" },
.{ .name = "DMA2_CH5", .index = 60, .description = "DMA2_CH5" },
.{ .name = "UCPD1", .index = 63, .description = "UCPD1" },
.{ .name = "COMP1_2_3", .index = 64, .description = "COMP1_2_3" },
.{ .name = "COMP4_5_6", .index = 65, .description = "COMP4_5_6" },
.{ .name = "COMP7", .index = 66, .description = "COMP7" },
.{ .name = "CRS", .index = 75, .description = "CRS" },
.{ .name = "SAI", .index = 76, .description = "SAI" },
.{ .name = "TIM20_BRK", .index = 77, .description = "TIM20_BRK" },
.{ .name = "TIM20_UP", .index = 78, .description = "TIM20_UP" },
.{ .name = "TIM20_TRG_COM", .index = 79, .description = "TIM20_TRG_COM" },
.{ .name = "TIM20_CC", .index = 80, .description = "TIM20_CC" },
.{ .name = "FPU", .index = 81, .description = "Floating point interrupt" },
.{ .name = "AES", .index = 85, .description = "AES" },
.{ .name = "RNG", .index = 90, .description = "RNG" },
.{ .name = "LPUART", .index = 91, .description = "LPUART" },
.{ .name = "I2C3_EV", .index = 92, .description = "I2C3_EV" },
.{ .name = "I2C3_ER", .index = 93, .description = "I2C3_ER" },
.{ .name = "DMAMUX_OVR", .index = 94, .description = "DMAMUX_OVR" },
.{ .name = "DMA2_CH6", .index = 97, .description = "DMA2_CH6" },
.{ .name = "Cordic", .index = 100, .description = "Cordic" },
.{ .name = "FMAC", .index = 101, .description = "FMAC" },
};
pub const VectorTable = extern struct {
const Handler = microzig.interrupt.Handler;
const unhandled = microzig.interrupt.unhandled;
initial_stack_pointer: *const anyopaque,
Reset: Handler,
NMI: Handler = unhandled,
HardFault: Handler = unhandled,
MemManageFault: Handler = unhandled,
BusFault: Handler = unhandled,
UsageFault: Handler = unhandled,
reserved5: [4]u32 = undefined,
SVCall: Handler = unhandled,
reserved10: [2]u32 = undefined,
PendSV: Handler = unhandled,
SysTick: Handler = unhandled,
/// Window Watchdog interrupt
WWDG: Handler = unhandled,
/// PVD through EXTI line detection
PVD_PVM: Handler = unhandled,
/// RTC_TAMP_CSS_LSE
RTC_TAMP_CSS_LSE: Handler = unhandled,
/// RTC Wakeup timer
RTC_WKUP: Handler = unhandled,
/// FLASH
FLASH: Handler = unhandled,
/// RCC global interrupt
RCC: Handler = unhandled,
/// EXTI Line0 interrupt
EXTI0: Handler = unhandled,
/// EXTI Line1 interrupt
EXTI1: Handler = unhandled,
/// EXTI Line2 interrupt
EXTI2: Handler = unhandled,
/// EXTI Line3 interrupt
EXTI3: Handler = unhandled,
/// EXTI Line4 interrupt
EXTI4: Handler = unhandled,
/// DMA1 channel 1 interrupt
DMA1_CH1: Handler = unhandled,
/// DMA1 channel 2 interrupt
DMA1_CH2: Handler = unhandled,
/// DMA1 channel 3 interrupt
DMA1_CH3: Handler = unhandled,
/// DMA1 channel 4 interrupt
DMA1_CH4: Handler = unhandled,
/// DMA1 channel 5 interrupt
DMA1_CH5: Handler = unhandled,
/// DMA1 channel 6 interrupt
DMA1_CH6: Handler = unhandled,
reserved31: [1]u32 = undefined,
/// ADC1 and ADC2 global interrupt
ADC1_2: Handler = unhandled,
/// USB_HP
USB_HP: Handler = unhandled,
/// USB_LP
USB_LP: Handler = unhandled,
/// FDCAN1 interrupt 0
FDCAN1_IT0: Handler = unhandled,
/// FDCAN1 interrupt 1
FDCAN1_IT1: Handler = unhandled,
/// EXTI9_5
EXTI9_5: Handler = unhandled,
/// TIM1_BRK_TIM15
TIM1_BRK_TIM15: Handler = unhandled,
/// TIM1_UP_TIM16
TIM1_UP_TIM16: Handler = unhandled,
/// TIM1_TRG_COM/
TIM1_TRG_COM: Handler = unhandled,
/// TIM1 capture compare interrupt
TIM1_CC: Handler = unhandled,
/// TIM2
TIM2: Handler = unhandled,
/// TIM3
TIM3: Handler = unhandled,
/// TIM4
TIM4: Handler = unhandled,
/// I2C1_EV
I2C1_EV: Handler = unhandled,
/// I2C1_ER
I2C1_ER: Handler = unhandled,
/// I2C2_EV
I2C2_EV: Handler = unhandled,
/// I2C2_ER
I2C2_ER: Handler = unhandled,
/// SPI1
SPI1: Handler = unhandled,
/// SPI2
SPI2: Handler = unhandled,
/// USART1
USART1: Handler = unhandled,
/// USART2
USART2: Handler = unhandled,
/// USART3
USART3: Handler = unhandled,
/// EXTI15_10
EXTI15_10: Handler = unhandled,
/// RTC_ALARM
RTC_ALARM: Handler = unhandled,
/// USBWakeUP
USBWakeUP: Handler = unhandled,
/// TIM8_BRK
TIM8_BRK: Handler = unhandled,
/// TIM8_UP
TIM8_UP: Handler = unhandled,
/// TIM8_TRG_COM
TIM8_TRG_COM: Handler = unhandled,
/// TIM8_CC
TIM8_CC: Handler = unhandled,
reserved61: [2]u32 = undefined,
/// LPTIM1
LPTIM1: Handler = unhandled,
reserved64: [1]u32 = undefined,
/// SPI3
SPI3: Handler = unhandled,
/// UART4
UART4: Handler = unhandled,
reserved67: [1]u32 = undefined,
/// TIM6_DACUNDER
TIM6_DACUNDER: Handler = unhandled,
/// TIM7
TIM7: Handler = unhandled,
/// DMA2_CH1
DMA2_CH1: Handler = unhandled,
/// DMA2_CH2
DMA2_CH2: Handler = unhandled,
/// DMA2_CH3
DMA2_CH3: Handler = unhandled,
/// DMA2_CH4
DMA2_CH4: Handler = unhandled,
/// DMA2_CH5
DMA2_CH5: Handler = unhandled,
reserved75: [2]u32 = undefined,
/// UCPD1
UCPD1: Handler = unhandled,
/// COMP1_2_3
COMP1_2_3: Handler = unhandled,
/// COMP4_5_6
COMP4_5_6: Handler = unhandled,
/// COMP7
COMP7: Handler = unhandled,
reserved81: [8]u32 = undefined,
/// CRS
CRS: Handler = unhandled,
/// SAI
SAI: Handler = unhandled,
/// TIM20_BRK
TIM20_BRK: Handler = unhandled,
/// TIM20_UP
TIM20_UP: Handler = unhandled,
/// TIM20_TRG_COM
TIM20_TRG_COM: Handler = unhandled,
/// TIM20_CC
TIM20_CC: Handler = unhandled,
/// Floating point interrupt
FPU: Handler = unhandled,
reserved96: [3]u32 = undefined,
/// AES
AES: Handler = unhandled,
reserved100: [4]u32 = undefined,
/// RNG
RNG: Handler = unhandled,
/// LPUART
LPUART: Handler = unhandled,
/// I2C3_EV
I2C3_EV: Handler = unhandled,
/// I2C3_ER
I2C3_ER: Handler = unhandled,
/// DMAMUX_OVR
DMAMUX_OVR: Handler = unhandled,
reserved109: [2]u32 = undefined,
/// DMA2_CH6
DMA2_CH6: Handler = unhandled,
reserved112: [2]u32 = undefined,
/// Cordic
Cordic: Handler = unhandled,
/// FMAC
FMAC: Handler = unhandled,
};
pub const peripherals = struct {
/// Advanced-timers
pub const TIM2: *volatile types.peripherals.TIM2 = @ptrFromInt(0x40000000);
/// Advanced-timers
pub const TIM3: *volatile types.peripherals.TIM3 = @ptrFromInt(0x40000400);
/// Advanced-timers
pub const TIM4: *volatile types.peripherals.TIM3 = @ptrFromInt(0x40000800);
/// Basic-timers
pub const TIM6: *volatile types.peripherals.TIM6 = @ptrFromInt(0x40001000);
/// Basic-timers
pub const TIM7: *volatile types.peripherals.TIM6 = @ptrFromInt(0x40001400);
/// CRS
pub const CRS: *volatile types.peripherals.CRS = @ptrFromInt(0x40002000);
/// Tamper and backup registers
pub const TAMP: *volatile types.peripherals.TAMP = @ptrFromInt(0x40002400);
/// Real-time clock
pub const RTC: *volatile types.peripherals.RTC = @ptrFromInt(0x40002800);
/// System window watchdog
pub const WWDG: *volatile types.peripherals.WWDG = @ptrFromInt(0x40002c00);
/// WinWATCHDOG
pub const IWDG: *volatile types.peripherals.IWDG = @ptrFromInt(0x40003000);
/// Serial peripheral interface/Inter-IC sound
pub const SPI2: *volatile types.peripherals.SPI1 = @ptrFromInt(0x40003800);
/// Serial peripheral interface/Inter-IC sound
pub const SPI3: *volatile types.peripherals.SPI1 = @ptrFromInt(0x40003c00);
/// Universal synchronous asynchronous receiver transmitter
pub const USART2: *volatile types.peripherals.USART1 = @ptrFromInt(0x40004400);
/// Universal synchronous asynchronous receiver transmitter
pub const USART3: *volatile types.peripherals.USART1 = @ptrFromInt(0x40004800);
/// Universal synchronous asynchronous receiver transmitter
pub const UART4: *volatile types.peripherals.UART4 = @ptrFromInt(0x40004c00);
/// Inter-integrated circuit
pub const I2C1: *volatile types.peripherals.I2C1 = @ptrFromInt(0x40005400);
/// Inter-integrated circuit
pub const I2C2: *volatile types.peripherals.I2C1 = @ptrFromInt(0x40005800);
/// USB_FS_device
pub const USB_FS_device: *volatile types.peripherals.USB_FS_device = @ptrFromInt(0x40005c00);
/// FDCAN
pub const FDCAN1: *volatile types.peripherals.FDCAN = @ptrFromInt(0x40006400);
/// Power control
pub const PWR: *volatile types.peripherals.PWR = @ptrFromInt(0x40007000);
/// Inter-integrated circuit
pub const I2C3: *volatile types.peripherals.I2C1 = @ptrFromInt(0x40007800);
/// Low power timer
pub const LPTIM1: *volatile types.peripherals.LPTIM1 = @ptrFromInt(0x40007c00);
/// Universal synchronous asynchronous receiver transmitter
pub const LPUART1: *volatile types.peripherals.LPUART1 = @ptrFromInt(0x40008000);
/// UCPD1
pub const UCPD1: *volatile types.peripherals.UCPD1 = @ptrFromInt(0x4000a000);
/// FDCAN
pub const FDCAN: *volatile types.peripherals.FDCAN = @ptrFromInt(0x4000a400);
/// System configuration controller
pub const SYSCFG: *volatile types.peripherals.SYSCFG = @ptrFromInt(0x40010000);
/// Voltage reference buffer
pub const VREFBUF: *volatile types.peripherals.VREFBUF = @ptrFromInt(0x40010030);
/// Comparator control and status register
pub const COMP: *volatile types.peripherals.COMP = @ptrFromInt(0x40010200);
/// Operational amplifiers
pub const OPAMP: *volatile types.peripherals.OPAMP = @ptrFromInt(0x40010300);
/// External interrupt/event controller
pub const EXTI: *volatile types.peripherals.EXTI = @ptrFromInt(0x40010400);
/// Advanced-timers
pub const TIM1: *volatile types.peripherals.TIM1 = @ptrFromInt(0x40012c00);
/// Serial peripheral interface/Inter-IC sound
pub const SPI1: *volatile types.peripherals.SPI1 = @ptrFromInt(0x40013000);
/// Advanced-timers
pub const TIM8: *volatile types.peripherals.TIM1 = @ptrFromInt(0x40013400);
/// Universal synchronous asynchronous receiver transmitter
pub const USART1: *volatile types.peripherals.USART1 = @ptrFromInt(0x40013800);
/// General purpose timers
pub const TIM15: *volatile types.peripherals.TIM15 = @ptrFromInt(0x40014000);
/// General purpose timers
pub const TIM16: *volatile types.peripherals.TIM16 = @ptrFromInt(0x40014400);
/// General purpose timers
pub const TIM17: *volatile types.peripherals.TIM16 = @ptrFromInt(0x40014800);
/// Advanced-timers
pub const TIM20: *volatile types.peripherals.TIM1 = @ptrFromInt(0x40015000);
/// Serial audio interface
pub const SAI: *volatile types.peripherals.SAI = @ptrFromInt(0x40015400);
/// DMA controller
pub const DMA1: *volatile types.peripherals.DMA1 = @ptrFromInt(0x40020000);
/// DMA controller
pub const DMA2: *volatile types.peripherals.DMA1 = @ptrFromInt(0x40020400);
/// DMAMUX
pub const DMAMUX: *volatile types.peripherals.DMAMUX = @ptrFromInt(0x40020800);
/// CORDIC Co-processor
pub const CORDIC: *volatile types.peripherals.CORDIC = @ptrFromInt(0x40020c00);
/// Reset and clock control
pub const RCC: *volatile types.peripherals.RCC = @ptrFromInt(0x40021000);
/// Filter Math Accelerator
pub const FMAC: *volatile types.peripherals.FMAC = @ptrFromInt(0x40021400);
/// Flash
pub const FLASH: *volatile types.peripherals.FLASH = @ptrFromInt(0x40022000);
/// Cyclic redundancy check calculation unit
pub const CRC: *volatile types.peripherals.CRC = @ptrFromInt(0x40023000);
/// General-purpose I/Os
pub const GPIOA: *volatile types.peripherals.GPIOA = @ptrFromInt(0x48000000);
/// General-purpose I/Os
pub const GPIOB: *volatile types.peripherals.GPIOB = @ptrFromInt(0x48000400);
/// General-purpose I/Os
pub const GPIOC: *volatile types.peripherals.GPIOC = @ptrFromInt(0x48000800);
/// General-purpose I/Os
pub const GPIOD: *volatile types.peripherals.GPIOC = @ptrFromInt(0x48000c00);
/// General-purpose I/Os
pub const GPIOE: *volatile types.peripherals.GPIOC = @ptrFromInt(0x48001000);
/// General-purpose I/Os
pub const GPIOF: *volatile types.peripherals.GPIOC = @ptrFromInt(0x48001400);
/// General-purpose I/Os
pub const GPIOG: *volatile types.peripherals.GPIOC = @ptrFromInt(0x48001800);
/// Analog-to-Digital Converter
pub const ADC1: *volatile types.peripherals.ADC1 = @ptrFromInt(0x50000000);
/// Analog-to-Digital Converter
pub const ADC2: *volatile types.peripherals.ADC1 = @ptrFromInt(0x50000100);
/// Analog-to-Digital Converter
pub const ADC12_Common: *volatile types.peripherals.ADC12_Common = @ptrFromInt(0x50000300);
/// Analog-to-Digital Converter
pub const ADC345_Common: *volatile types.peripherals.ADC12_Common = @ptrFromInt(0x50000700);
/// Digital-to-analog converter
pub const DAC1: *volatile types.peripherals.DAC1 = @ptrFromInt(0x50000800);
/// Digital-to-analog converter
pub const DAC2: *volatile types.peripherals.DAC1 = @ptrFromInt(0x50000c00);
/// Digital-to-analog converter
pub const DAC3: *volatile types.peripherals.DAC1 = @ptrFromInt(0x50001000);
/// Digital-to-analog converter
pub const DAC4: *volatile types.peripherals.DAC1 = @ptrFromInt(0x50001400);
/// Advanced encryption standard hardware accelerator
pub const AES: *volatile types.peripherals.AES = @ptrFromInt(0x50060000);
/// Random number generator
pub const RNG: *volatile types.peripherals.RNG = @ptrFromInt(0x50060800);
/// Debug support
pub const DBGMCU: *volatile types.peripherals.DBGMCU = @ptrFromInt(0xe0042000);
};

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pub const peripherals = @import("types/peripherals.zig");

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pub const ADC1 = @import("peripherals/ADC1.zig").ADC1;
pub const ADC12_Common = @import("peripherals/ADC12_Common.zig").ADC12_Common;
pub const AES = @import("peripherals/AES.zig").AES;
pub const COMP = @import("peripherals/COMP.zig").COMP;
pub const CORDIC = @import("peripherals/CORDIC.zig").CORDIC;
pub const CRC = @import("peripherals/CRC.zig").CRC;
pub const CRS = @import("peripherals/CRS.zig").CRS;
pub const DAC1 = @import("peripherals/DAC1.zig").DAC1;
pub const DBGMCU = @import("peripherals/DBGMCU.zig").DBGMCU;
pub const DMA1 = @import("peripherals/DMA1.zig").DMA1;
pub const DMAMUX = @import("peripherals/DMAMUX.zig").DMAMUX;
pub const EXTI = @import("peripherals/EXTI.zig").EXTI;
pub const FDCAN = @import("peripherals/FDCAN.zig").FDCAN;
pub const FLASH = @import("peripherals/FLASH.zig").FLASH;
pub const FMAC = @import("peripherals/FMAC.zig").FMAC;
pub const GPIOA = @import("peripherals/GPIOA.zig").GPIOA;
pub const GPIOB = @import("peripherals/GPIOB.zig").GPIOB;
pub const GPIOC = @import("peripherals/GPIOC.zig").GPIOC;
pub const I2C1 = @import("peripherals/I2C1.zig").I2C1;
pub const IWDG = @import("peripherals/IWDG.zig").IWDG;
pub const LPTIM1 = @import("peripherals/LPTIM1.zig").LPTIM1;
pub const LPUART1 = @import("peripherals/LPUART1.zig").LPUART1;
pub const OPAMP = @import("peripherals/OPAMP.zig").OPAMP;
pub const PWR = @import("peripherals/PWR.zig").PWR;
pub const RCC = @import("peripherals/RCC.zig").RCC;
pub const RNG = @import("peripherals/RNG.zig").RNG;
pub const RTC = @import("peripherals/RTC.zig").RTC;
pub const SAI = @import("peripherals/SAI.zig").SAI;
pub const SPI1 = @import("peripherals/SPI1.zig").SPI1;
pub const SYSCFG = @import("peripherals/SYSCFG.zig").SYSCFG;
pub const TAMP = @import("peripherals/TAMP.zig").TAMP;
pub const TIM1 = @import("peripherals/TIM1.zig").TIM1;
pub const TIM15 = @import("peripherals/TIM15.zig").TIM15;
pub const TIM16 = @import("peripherals/TIM16.zig").TIM16;
pub const TIM2 = @import("peripherals/TIM2.zig").TIM2;
pub const TIM3 = @import("peripherals/TIM3.zig").TIM3;
pub const TIM6 = @import("peripherals/TIM6.zig").TIM6;
pub const UART4 = @import("peripherals/UART4.zig").UART4;
pub const UCPD1 = @import("peripherals/UCPD1.zig").UCPD1;
pub const USART1 = @import("peripherals/USART1.zig").USART1;
pub const USB_FS_device = @import("peripherals/USB_FS_device.zig").USB_FS_device;
pub const VREFBUF = @import("peripherals/VREFBUF.zig").VREFBUF;
pub const WWDG = @import("peripherals/WWDG.zig").WWDG;

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const microzig = @import("microzig");
const mmio = microzig.mmio;
const types = @import("../../types.zig");
/// Analog-to-Digital Converter
pub const ADC1 = extern struct {
/// interrupt and status register
/// offset: 0x00
ISR: mmio.Mmio(packed struct(u32) {
/// ADRDY
ADRDY: u1 = 0x0,
/// EOSMP
EOSMP: u1 = 0x0,
/// EOC
EOC: u1 = 0x0,
/// EOS
EOS: u1 = 0x0,
/// OVR
OVR: u1 = 0x0,
/// JEOC
JEOC: u1 = 0x0,
/// JEOS
JEOS: u1 = 0x0,
/// AWD1
AWD1: u1 = 0x0,
/// AWD2
AWD2: u1 = 0x0,
/// AWD3
AWD3: u1 = 0x0,
/// JQOVF
JQOVF: u1 = 0x0,
padding: u21 = 0,
}),
/// interrupt enable register
/// offset: 0x04
IER: mmio.Mmio(packed struct(u32) {
/// ADRDYIE
ADRDYIE: u1 = 0x0,
/// EOSMPIE
EOSMPIE: u1 = 0x0,
/// EOCIE
EOCIE: u1 = 0x0,
/// EOSIE
EOSIE: u1 = 0x0,
/// OVRIE
OVRIE: u1 = 0x0,
/// JEOCIE
JEOCIE: u1 = 0x0,
/// JEOSIE
JEOSIE: u1 = 0x0,
/// AWD1IE
AWD1IE: u1 = 0x0,
/// AWD2IE
AWD2IE: u1 = 0x0,
/// AWD3IE
AWD3IE: u1 = 0x0,
/// JQOVFIE
JQOVFIE: u1 = 0x0,
padding: u21 = 0,
}),
/// control register
/// offset: 0x08
CR: mmio.Mmio(packed struct(u32) {
/// ADEN
ADEN: u1 = 0x0,
/// ADDIS
ADDIS: u1 = 0x0,
/// ADSTART
ADSTART: u1 = 0x0,
/// JADSTART
JADSTART: u1 = 0x0,
/// ADSTP
ADSTP: u1 = 0x0,
/// JADSTP
JADSTP: u1 = 0x0,
reserved28: u22 = 0,
/// ADVREGEN
ADVREGEN: u1 = 0x0,
/// DEEPPWD
DEEPPWD: u1 = 0x1,
/// ADCALDIF
ADCALDIF: u1 = 0x0,
/// ADCAL
ADCAL: u1 = 0x0,
}),
/// configuration register
/// offset: 0x0c
CFGR: mmio.Mmio(packed struct(u32) {
/// DMAEN
DMAEN: u1 = 0x0,
/// DMACFG
DMACFG: u1 = 0x0,
reserved3: u1 = 0,
/// RES
RES: u2 = 0x0,
/// External trigger selection for regular group
EXTSEL: u5 = 0x0,
/// EXTEN
EXTEN: u2 = 0x0,
/// OVRMOD
OVRMOD: u1 = 0x0,
/// CONT
CONT: u1 = 0x0,
/// AUTDLY
AUTDLY: u1 = 0x0,
/// ALIGN
ALIGN: u1 = 0x0,
/// DISCEN
DISCEN: u1 = 0x0,
/// DISCNUM
DISCNUM: u3 = 0x0,
/// JDISCEN
JDISCEN: u1 = 0x0,
/// JQM
JQM: u1 = 0x0,
/// AWD1SGL
AWD1SGL: u1 = 0x0,
/// AWD1EN
AWD1EN: u1 = 0x0,
/// JAWD1EN
JAWD1EN: u1 = 0x0,
/// JAUTO
JAUTO: u1 = 0x0,
/// Analog watchdog 1 channel selection
AWD1CH: u5 = 0x0,
/// Injected Queue disable
JQDIS: u1 = 0x1,
}),
/// configuration register
/// offset: 0x10
CFGR2: mmio.Mmio(packed struct(u32) {
/// DMAEN
ROVSE: u1 = 0x0,
/// DMACFG
JOVSE: u1 = 0x0,
/// RES
OVSR: u3 = 0x0,
/// ALIGN
OVSS: u4 = 0x0,
/// Triggered Regular Oversampling
TROVS: u1 = 0x0,
/// EXTEN
ROVSM: u1 = 0x0,
reserved16: u5 = 0,
/// GCOMP
GCOMP: u1 = 0x0,
reserved25: u8 = 0,
/// SWTRIG
SWTRIG: u1 = 0x0,
/// BULB
BULB: u1 = 0x0,
/// SMPTRIG
SMPTRIG: u1 = 0x0,
padding: u4 = 0,
}),
/// sample time register 1
/// offset: 0x14
SMPR1: mmio.Mmio(packed struct(u32) {
/// SMP0
SMP0: u3 = 0x0,
/// SMP1
SMP1: u3 = 0x0,
/// SMP2
SMP2: u3 = 0x0,
/// SMP3
SMP3: u3 = 0x0,
/// SMP4
SMP4: u3 = 0x0,
/// SMP5
SMP5: u3 = 0x0,
/// SMP6
SMP6: u3 = 0x0,
/// SMP7
SMP7: u3 = 0x0,
/// SMP8
SMP8: u3 = 0x0,
/// SMP9
SMP9: u3 = 0x0,
reserved31: u1 = 0,
/// Addition of one clock cycle to the sampling time
SMPPLUS: u1 = 0x0,
}),
/// sample time register 2
/// offset: 0x18
SMPR2: mmio.Mmio(packed struct(u32) {
/// SMP10
SMP10: u3 = 0x0,
/// SMP11
SMP11: u3 = 0x0,
/// SMP12
SMP12: u3 = 0x0,
/// SMP13
SMP13: u3 = 0x0,
/// SMP14
SMP14: u3 = 0x0,
/// SMP15
SMP15: u3 = 0x0,
/// SMP16
SMP16: u3 = 0x0,
/// SMP17
SMP17: u3 = 0x0,
/// SMP18
SMP18: u3 = 0x0,
padding: u5 = 0,
}),
/// offset: 0x1c
reserved28: [4]u8,
/// watchdog threshold register 1
/// offset: 0x20
TR1: mmio.Mmio(packed struct(u32) {
/// LT1
LT1: u12 = 0x0,
/// AWDFILT
AWDFILT: u3 = 0x0,
reserved16: u1 = 0,
/// HT1
HT1: u12 = 0xFFF,
padding: u4 = 0,
}),
/// watchdog threshold register
/// offset: 0x24
TR2: mmio.Mmio(packed struct(u32) {
/// LT2
LT2: u8 = 0x0,
reserved16: u8 = 0,
/// HT2
HT2: u8 = 0xFF,
padding: u8 = 0,
}),
/// watchdog threshold register 3
/// offset: 0x28
TR3: mmio.Mmio(packed struct(u32) {
/// LT3
LT3: u8 = 0x0,
reserved16: u8 = 0,
/// HT3
HT3: u8 = 0xFF,
padding: u8 = 0,
}),
/// offset: 0x2c
reserved44: [4]u8,
/// regular sequence register 1
/// offset: 0x30
SQR1: mmio.Mmio(packed struct(u32) {
/// Regular channel sequence length
L: u4 = 0x0,
reserved6: u2 = 0,
/// SQ1
SQ1: u5 = 0x0,
reserved12: u1 = 0,
/// SQ2
SQ2: u5 = 0x0,
reserved18: u1 = 0,
/// SQ3
SQ3: u5 = 0x0,
reserved24: u1 = 0,
/// SQ4
SQ4: u5 = 0x0,
padding: u3 = 0,
}),
/// regular sequence register 2
/// offset: 0x34
SQR2: mmio.Mmio(packed struct(u32) {
/// SQ5
SQ5: u5 = 0x0,
reserved6: u1 = 0,
/// SQ6
SQ6: u5 = 0x0,
reserved12: u1 = 0,
/// SQ7
SQ7: u5 = 0x0,
reserved18: u1 = 0,
/// SQ8
SQ8: u5 = 0x0,
reserved24: u1 = 0,
/// SQ9
SQ9: u5 = 0x0,
padding: u3 = 0,
}),
/// regular sequence register 3
/// offset: 0x38
SQR3: mmio.Mmio(packed struct(u32) {
/// SQ10
SQ10: u5 = 0x0,
reserved6: u1 = 0,
/// SQ11
SQ11: u5 = 0x0,
reserved12: u1 = 0,
/// SQ12
SQ12: u5 = 0x0,
reserved18: u1 = 0,
/// SQ13
SQ13: u5 = 0x0,
reserved24: u1 = 0,
/// SQ14
SQ14: u5 = 0x0,
padding: u3 = 0,
}),
/// regular sequence register 4
/// offset: 0x3c
SQR4: mmio.Mmio(packed struct(u32) {
/// SQ15
SQ15: u5 = 0x0,
reserved6: u1 = 0,
/// SQ16
SQ16: u5 = 0x0,
padding: u21 = 0,
}),
/// regular Data Register
/// offset: 0x40
DR: mmio.Mmio(packed struct(u32) {
/// Regular Data converted
RDATA: u16 = 0x0,
padding: u16 = 0,
}),
/// offset: 0x44
reserved68: [8]u8,
/// injected sequence register
/// offset: 0x4c
JSQR: mmio.Mmio(packed struct(u32) {
/// JL
JL: u2 = 0x0,
/// JEXTSEL
JEXTSEL: u5 = 0x0,
/// JEXTEN
JEXTEN: u2 = 0x0,
/// JSQ1
JSQ1: u5 = 0x0,
reserved15: u1 = 0,
/// JSQ2
JSQ2: u5 = 0x0,
reserved21: u1 = 0,
/// JSQ3
JSQ3: u5 = 0x0,
reserved27: u1 = 0,
/// JSQ4
JSQ4: u5 = 0x0,
}),
/// offset: 0x50
reserved80: [16]u8,
/// offset register 1
/// offset: 0x60
OFR1: mmio.Mmio(packed struct(u32) {
/// OFFSET1
OFFSET1: u12 = 0x0,
reserved24: u12 = 0,
/// OFFSETPOS
OFFSETPOS: u1 = 0x0,
/// SATEN
SATEN: u1 = 0x0,
/// OFFSET1_CH
OFFSET1_CH: u5 = 0x0,
/// OFFSET1_EN
OFFSET1_EN: u1 = 0x0,
}),
/// offset register 2
/// offset: 0x64
OFR2: mmio.Mmio(packed struct(u32) {
/// OFFSET1
OFFSET1: u12 = 0x0,
reserved24: u12 = 0,
/// OFFSETPOS
OFFSETPOS: u1 = 0x0,
/// SATEN
SATEN: u1 = 0x0,
/// OFFSET1_CH
OFFSET1_CH: u5 = 0x0,
/// OFFSET1_EN
OFFSET1_EN: u1 = 0x0,
}),
/// offset register 3
/// offset: 0x68
OFR3: mmio.Mmio(packed struct(u32) {
/// OFFSET1
OFFSET1: u12 = 0x0,
reserved24: u12 = 0,
/// OFFSETPOS
OFFSETPOS: u1 = 0x0,
/// SATEN
SATEN: u1 = 0x0,
/// OFFSET1_CH
OFFSET1_CH: u5 = 0x0,
/// OFFSET1_EN
OFFSET1_EN: u1 = 0x0,
}),
/// offset register 4
/// offset: 0x6c
OFR4: mmio.Mmio(packed struct(u32) {
/// OFFSET1
OFFSET1: u12 = 0x0,
reserved24: u12 = 0,
/// OFFSETPOS
OFFSETPOS: u1 = 0x0,
/// SATEN
SATEN: u1 = 0x0,
/// OFFSET1_CH
OFFSET1_CH: u5 = 0x0,
/// OFFSET1_EN
OFFSET1_EN: u1 = 0x0,
}),
/// offset: 0x70
reserved112: [16]u8,
/// injected data register 1
/// offset: 0x80
JDR1: mmio.Mmio(packed struct(u32) {
/// JDATA1
JDATA1: u16 = 0x0,
padding: u16 = 0,
}),
/// injected data register 2
/// offset: 0x84
JDR2: mmio.Mmio(packed struct(u32) {
/// JDATA2
JDATA2: u16 = 0x0,
padding: u16 = 0,
}),
/// injected data register 3
/// offset: 0x88
JDR3: mmio.Mmio(packed struct(u32) {
/// JDATA3
JDATA3: u16 = 0x0,
padding: u16 = 0,
}),
/// injected data register 4
/// offset: 0x8c
JDR4: mmio.Mmio(packed struct(u32) {
/// JDATA4
JDATA4: u16 = 0x0,
padding: u16 = 0,
}),
/// offset: 0x90
reserved144: [16]u8,
/// Analog Watchdog 2 Configuration Register
/// offset: 0xa0
AWD2CR: mmio.Mmio(packed struct(u32) {
/// AWD2CH
AWD2CH: u19 = 0x0,
padding: u13 = 0,
}),
/// Analog Watchdog 3 Configuration Register
/// offset: 0xa4
AWD3CR: mmio.Mmio(packed struct(u32) {
/// AWD3CH
AWD3CH: u19 = 0x0,
padding: u13 = 0,
}),
/// offset: 0xa8
reserved168: [8]u8,
/// Differential Mode Selection Register 2
/// offset: 0xb0
DIFSEL: mmio.Mmio(packed struct(u32) {
/// Differential mode for channels 0
DIFSEL_0: u1 = 0x0,
/// Differential mode for channels 15 to 1
DIFSEL_1_18: u18 = 0x0,
padding: u13 = 0,
}),
/// Calibration Factors
/// offset: 0xb4
CALFACT: mmio.Mmio(packed struct(u32) {
/// CALFACT_S
CALFACT_S: u7 = 0x0,
reserved16: u9 = 0,
/// CALFACT_D
CALFACT_D: u7 = 0x0,
padding: u9 = 0,
}),
/// offset: 0xb8
reserved184: [8]u8,
/// Gain compensation Register
/// offset: 0xc0
GCOMP: mmio.Mmio(packed struct(u32) {
/// GCOMPCOEFF
GCOMPCOEFF: u14 = 0x0,
padding: u18 = 0,
}),
};

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const microzig = @import("microzig");
const mmio = microzig.mmio;
const types = @import("../../types.zig");
/// Analog-to-Digital Converter
pub const ADC12_Common = extern struct {
/// ADC Common status register
/// offset: 0x00
CSR: mmio.Mmio(packed struct(u32) {
/// ADDRDY_MST
ADDRDY_MST: u1 = 0x0,
/// EOSMP_MST
EOSMP_MST: u1 = 0x0,
/// EOC_MST
EOC_MST: u1 = 0x0,
/// EOS_MST
EOS_MST: u1 = 0x0,
/// OVR_MST
OVR_MST: u1 = 0x0,
/// JEOC_MST
JEOC_MST: u1 = 0x0,
/// JEOS_MST
JEOS_MST: u1 = 0x0,
/// AWD1_MST
AWD1_MST: u1 = 0x0,
/// AWD2_MST
AWD2_MST: u1 = 0x0,
/// AWD3_MST
AWD3_MST: u1 = 0x0,
/// JQOVF_MST
JQOVF_MST: u1 = 0x0,
reserved16: u5 = 0,
/// ADRDY_SLV
ADRDY_SLV: u1 = 0x0,
/// EOSMP_SLV
EOSMP_SLV: u1 = 0x0,
/// End of regular conversion of the slave ADC
EOC_SLV: u1 = 0x0,
/// End of regular sequence flag of the slave ADC
EOS_SLV: u1 = 0x0,
/// Overrun flag of the slave ADC
OVR_SLV: u1 = 0x0,
/// End of injected conversion flag of the slave ADC
JEOC_SLV: u1 = 0x0,
/// End of injected sequence flag of the slave ADC
JEOS_SLV: u1 = 0x0,
/// Analog watchdog 1 flag of the slave ADC
AWD1_SLV: u1 = 0x0,
/// Analog watchdog 2 flag of the slave ADC
AWD2_SLV: u1 = 0x0,
/// Analog watchdog 3 flag of the slave ADC
AWD3_SLV: u1 = 0x0,
/// Injected Context Queue Overflow flag of the slave ADC
JQOVF_SLV: u1 = 0x0,
padding: u5 = 0,
}),
/// offset: 0x04
reserved4: [4]u8,
/// ADC common control register
/// offset: 0x08
CCR: mmio.Mmio(packed struct(u32) {
/// Dual ADC mode selection
DUAL: u5 = 0x0,
reserved8: u3 = 0,
/// Delay between 2 sampling phases
DELAY: u4 = 0x0,
reserved13: u1 = 0,
/// DMA configuration (for multi-ADC mode)
DMACFG: u1 = 0x0,
/// Direct memory access mode for multi ADC mode
MDMA: u2 = 0x0,
/// ADC clock mode
CKMODE: u2 = 0x0,
/// ADC prescaler
PRESC: u4 = 0x0,
/// VREFINT enable
VREFEN: u1 = 0x0,
/// VTS selection
VSENSESEL: u1 = 0x0,
/// VBAT selection
VBATSEL: u1 = 0x0,
padding: u7 = 0,
}),
/// ADC common regular data register for dual and triple modes
/// offset: 0x0c
CDR: mmio.Mmio(packed struct(u32) {
/// Regular data of the master ADC
RDATA_MST: u16 = 0x0,
/// Regular data of the slave ADC
RDATA_SLV: u16 = 0x0,
}),
};

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src/stm32g4/types/peripherals/AES.zig Normal file
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const microzig = @import("microzig");
const mmio = microzig.mmio;
const types = @import("../../types.zig");
/// Advanced encryption standard hardware accelerator
pub const AES = extern struct {
/// control register
/// offset: 0x00
CR: mmio.Mmio(packed struct(u32) {
/// AES enable
EN: u1 = 0x0,
/// Data type selection (for data in and data out to/from the cryptographic block)
DATATYPE: u2 = 0x0,
/// AES operating mode
MODE: u2 = 0x0,
/// AES chaining mode
CHMOD: u2 = 0x0,
/// Computation Complete Flag Clear
CCFC: u1 = 0x0,
/// Error clear
ERRC: u1 = 0x0,
/// CCF flag interrupt enable
CCFIE: u1 = 0x0,
/// Error interrupt enable
ERRIE: u1 = 0x0,
/// Enable DMA management of data input phase
DMAINEN: u1 = 0x0,
/// Enable DMA management of data output phase
DMAOUTEN: u1 = 0x0,
/// GCMPH
GCMPH: u2 = 0x0,
reserved16: u1 = 0,
/// CHMOD_2
CHMOD_2: u1 = 0x0,
reserved18: u1 = 0,
/// KEYSIZE
KEYSIZE: u1 = 0x0,
reserved20: u1 = 0,
/// NPBLB
NPBLB: u4 = 0x0,
padding: u8 = 0,
}),
/// status register
/// offset: 0x04
SR: mmio.Mmio(packed struct(u32) {
/// Computation complete flag
CCF: u1 = 0x0,
/// Read error flag
RDERR: u1 = 0x0,
/// Write error flag
WRERR: u1 = 0x0,
/// BUSY
BUSY: u1 = 0x0,
padding: u28 = 0,
}),
/// data input register
/// offset: 0x08
DINR: mmio.Mmio(packed struct(u32) {
/// Data Input Register
AES_DINR: u32 = 0x0,
}),
/// data output register
/// offset: 0x0c
DOUTR: mmio.Mmio(packed struct(u32) {
/// Data output register
AES_DOUTR: u32 = 0x0,
}),
/// key register 0
/// offset: 0x10
KEYR0: mmio.Mmio(packed struct(u32) {
/// Data Output Register (LSB key [31:0])
AES_KEYR0: u32 = 0x0,
}),
/// key register 1
/// offset: 0x14
KEYR1: mmio.Mmio(packed struct(u32) {
/// AES key register (key [63:32])
AES_KEYR1: u32 = 0x0,
}),
/// key register 2
/// offset: 0x18
KEYR2: mmio.Mmio(packed struct(u32) {
/// AES key register (key [95:64])
AES_KEYR2: u32 = 0x0,
}),
/// key register 3
/// offset: 0x1c
KEYR3: mmio.Mmio(packed struct(u32) {
/// AES key register (MSB key [127:96])
AES_KEYR3: u32 = 0x0,
}),
/// initialization vector register 0
/// offset: 0x20
IVR0: mmio.Mmio(packed struct(u32) {
/// initialization vector register (LSB IVR [31:0])
AES_IVR0: u32 = 0x0,
}),
/// initialization vector register 1
/// offset: 0x24
IVR1: mmio.Mmio(packed struct(u32) {
/// Initialization Vector Register (IVR [63:32])
AES_IVR1: u32 = 0x0,
}),
/// initialization vector register 2
/// offset: 0x28
IVR2: mmio.Mmio(packed struct(u32) {
/// Initialization Vector Register (IVR [95:64])
AES_IVR2: u32 = 0x0,
}),
/// initialization vector register 3
/// offset: 0x2c
IVR3: mmio.Mmio(packed struct(u32) {
/// Initialization Vector Register (MSB IVR [127:96])
AES_IVR3: u32 = 0x0,
}),
/// key register 4
/// offset: 0x30
KEYR4: mmio.Mmio(packed struct(u32) {
/// AES key
KEY: u32 = 0x0,
}),
/// key register 5
/// offset: 0x34
KEYR5: mmio.Mmio(packed struct(u32) {
/// AES key
KEY: u32 = 0x0,
}),
/// key register 6
/// offset: 0x38
KEYR6: mmio.Mmio(packed struct(u32) {
/// AES key
KEY: u32 = 0x0,
}),
/// key register 7
/// offset: 0x3c
KEYR7: mmio.Mmio(packed struct(u32) {
/// AES key
KEY: u32 = 0x0,
}),
/// suspend registers
/// offset: 0x40
SUSP0R: mmio.Mmio(packed struct(u32) {
/// AES suspend
SUSP: u32 = 0x0,
}),
/// suspend registers
/// offset: 0x44
SUSP1R: mmio.Mmio(packed struct(u32) {
/// AES suspend
SUSP: u32 = 0x0,
}),
/// suspend registers
/// offset: 0x48
SUSP2R: mmio.Mmio(packed struct(u32) {
/// AES suspend
SUSP: u32 = 0x0,
}),
/// suspend registers
/// offset: 0x4c
SUSP3R: mmio.Mmio(packed struct(u32) {
/// AES suspend
SUSP: u32 = 0x0,
}),
/// suspend registers
/// offset: 0x50
SUSP4R: mmio.Mmio(packed struct(u32) {
/// AES suspend
SUSP: u32 = 0x0,
}),
/// suspend registers
/// offset: 0x54
SUSP5R: mmio.Mmio(packed struct(u32) {
/// AES suspend
SUSP: u32 = 0x0,
}),
/// suspend registers
/// offset: 0x58
SUSP6R: mmio.Mmio(packed struct(u32) {
/// AES suspend
SUSP: u32 = 0x0,
}),
/// suspend registers
/// offset: 0x5c
SUSP7R: mmio.Mmio(packed struct(u32) {
/// AES suspend
SUSP: u32 = 0x0,
}),
};

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const microzig = @import("microzig");
const mmio = microzig.mmio;
const types = @import("../../types.zig");
/// Comparator control and status register
pub const COMP = extern struct {
/// Comparator control/status register
/// offset: 0x00
COMP_C1CSR: mmio.Mmio(packed struct(u32) {
/// EN
EN: u1 = 0x0,
reserved4: u3 = 0,
/// INMSEL
INMSEL: u3 = 0x0,
reserved8: u1 = 0,
/// INPSEL
INPSEL: u1 = 0x0,
reserved15: u6 = 0,
/// POL
POL: u1 = 0x0,
/// HYST
HYST: u3 = 0x0,
/// BLANKSEL
BLANKSEL: u3 = 0x0,
/// BRGEN
BRGEN: u1 = 0x0,
/// SCALEN
SCALEN: u1 = 0x0,
reserved30: u6 = 0,
/// VALUE
VALUE: u1 = 0x0,
/// LOCK
LOCK: u1 = 0x0,
}),
/// Comparator control/status register
/// offset: 0x04
COMP_C2CSR: mmio.Mmio(packed struct(u32) {
/// EN
EN: u1 = 0x0,
reserved4: u3 = 0,
/// INMSEL
INMSEL: u3 = 0x0,
reserved8: u1 = 0,
/// INPSEL
INPSEL: u1 = 0x0,
reserved15: u6 = 0,
/// POL
POL: u1 = 0x0,
/// HYST
HYST: u3 = 0x0,
/// BLANKSEL
BLANKSEL: u3 = 0x0,
/// BRGEN
BRGEN: u1 = 0x0,
/// SCALEN
SCALEN: u1 = 0x0,
reserved30: u6 = 0,
/// VALUE
VALUE: u1 = 0x0,
/// LOCK
LOCK: u1 = 0x0,
}),
/// Comparator control/status register
/// offset: 0x08
COMP_C3CSR: mmio.Mmio(packed struct(u32) {
/// EN
EN: u1 = 0x0,
reserved4: u3 = 0,
/// INMSEL
INMSEL: u3 = 0x0,
reserved8: u1 = 0,
/// INPSEL
INPSEL: u1 = 0x0,
reserved15: u6 = 0,
/// POL
POL: u1 = 0x0,
/// HYST
HYST: u3 = 0x0,
/// BLANKSEL
BLANKSEL: u3 = 0x0,
/// BRGEN
BRGEN: u1 = 0x0,
/// SCALEN
SCALEN: u1 = 0x0,
reserved30: u6 = 0,
/// VALUE
VALUE: u1 = 0x0,
/// LOCK
LOCK: u1 = 0x0,
}),
/// Comparator control/status register
/// offset: 0x0c
COMP_C4CSR: mmio.Mmio(packed struct(u32) {
/// EN
EN: u1 = 0x0,
reserved4: u3 = 0,
/// INMSEL
INMSEL: u3 = 0x0,
reserved8: u1 = 0,
/// INPSEL
INPSEL: u1 = 0x0,
reserved15: u6 = 0,
/// POL
POL: u1 = 0x0,
/// HYST
HYST: u3 = 0x0,
/// BLANKSEL
BLANKSEL: u3 = 0x0,
/// BRGEN
BRGEN: u1 = 0x0,
/// SCALEN
SCALEN: u1 = 0x0,
reserved30: u6 = 0,
/// VALUE
VALUE: u1 = 0x0,
/// LOCK
LOCK: u1 = 0x0,
}),
};

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src/stm32g4/types/peripherals/CORDIC.zig Normal file
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const microzig = @import("microzig");
const mmio = microzig.mmio;
const types = @import("../../types.zig");
/// CORDIC Co-processor
pub const CORDIC = extern struct {
/// CORDIC Control Status register
/// offset: 0x00
CSR: mmio.Mmio(packed struct(u32) {
/// FUNC
FUNC: u4 = 0x0,
/// PRECISION
PRECISION: u4 = 0x0,
/// SCALE
SCALE: u3 = 0x0,
reserved16: u5 = 0,
/// IEN
IEN: u1 = 0x0,
/// DMAREN
DMAREN: u1 = 0x0,
/// DMAWEN
DMAWEN: u1 = 0x0,
/// NRES
NRES: u1 = 0x0,
/// NARGS
NARGS: u1 = 0x0,
/// RESSIZE
RESSIZE: u1 = 0x0,
/// ARGSIZE
ARGSIZE: u1 = 0x0,
reserved31: u8 = 0,
/// RRDY
RRDY: u1 = 0x0,
}),
/// FMAC Write Data register
/// offset: 0x04
WDATA: mmio.Mmio(packed struct(u32) {
/// ARG
ARG: u32 = 0x0,
}),
/// FMAC Read Data register
/// offset: 0x08
RDATA: mmio.Mmio(packed struct(u32) {
/// RES
RES: u32 = 0x0,
}),
};

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src/stm32g4/types/peripherals/CRC.zig Normal file
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const microzig = @import("microzig");
const mmio = microzig.mmio;
const types = @import("../../types.zig");
/// Cyclic redundancy check calculation unit
pub const CRC = extern struct {
/// Data register
/// offset: 0x00
DR: mmio.Mmio(packed struct(u32) {
/// Data register bits
DR: u32 = 0xFFFFFFFF,
}),
/// Independent data register
/// offset: 0x04
IDR: mmio.Mmio(packed struct(u32) {
/// General-purpose 8-bit data register bits
IDR: u32 = 0x0,
}),
/// Control register
/// offset: 0x08
CR: mmio.Mmio(packed struct(u32) {
/// RESET bit
RESET: u1 = 0x0,
reserved3: u2 = 0,
/// Polynomial size
POLYSIZE: u2 = 0x0,
/// Reverse input data
REV_IN: u2 = 0x0,
/// Reverse output data
REV_OUT: u1 = 0x0,
padding: u24 = 0,
}),
/// offset: 0x0c
reserved12: [4]u8,
/// Initial CRC value
/// offset: 0x10
INIT: mmio.Mmio(packed struct(u32) {
/// Programmable initial CRC value
CRC_INIT: u32 = 0xFFFFFFFF,
}),
/// polynomial
/// offset: 0x14
POL: mmio.Mmio(packed struct(u32) {
/// Programmable polynomial
POL: u32 = 0x4C11DB7,
}),
};

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src/stm32g4/types/peripherals/CRS.zig Normal file
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const microzig = @import("microzig");
const mmio = microzig.mmio;
const types = @import("../../types.zig");
/// CRS
pub const CRS = extern struct {
/// CRS control register
/// offset: 0x00
CR: mmio.Mmio(packed struct(u32) {
/// SYNC event OK interrupt enable
SYNCOKIE: u1 = 0x0,
/// SYNC warning interrupt enable
SYNCWARNIE: u1 = 0x0,
/// Synchronization or trimming error interrupt enable
ERRIE: u1 = 0x0,
/// Expected SYNC interrupt enable
ESYNCIE: u1 = 0x0,
reserved5: u1 = 0,
/// Frequency error counter enable This bit enables the oscillator clock for the frequency error counter. When this bit is set, the CRS_CFGR register is write-protected and cannot be modified.
CEN: u1 = 0x0,
/// Automatic trimming enable This bit enables the automatic hardware adjustment of TRIM bits according to the measured frequency error between two SYNC events. If this bit is set, the TRIM bits are read-only. The TRIM value can be adjusted by hardware by one or two steps at a time, depending on the measured frequency error value. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details.
AUTOTRIMEN: u1 = 0x0,
/// Generate software SYNC event This bit is set by software in order to generate a software SYNC event. It is automatically cleared by hardware.
SWSYNC: u1 = 0x0,
/// HSI48 oscillator smooth trimming These bits provide a user-programmable trimming value to the HSI48 oscillator. They can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI48. The default value is 32, which corresponds to the middle of the trimming interval. The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value corresponds to a higher output frequency. When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only.
TRIM: u7 = 0x40,
padding: u17 = 0,
}),
/// This register can be written only when the frequency error counter is disabled (CEN bit is cleared in CRS_CR). When the counter is enabled, this register is write-protected.
/// offset: 0x04
CFGR: mmio.Mmio(packed struct(u32) {
/// Counter reload value RELOAD is the value to be loaded in the frequency error counter with each SYNC event. Refer to Section7.3.3: Frequency error measurement for more details about counter behavior.
RELOAD: u16 = 0xBB7F,
/// Frequency error limit FELIM contains the value to be used to evaluate the captured frequency error value latched in the FECAP[15:0] bits of the CRS_ISR register. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details about FECAP evaluation.
FELIM: u8 = 0x22,
/// SYNC divider These bits are set and cleared by software to control the division factor of the SYNC signal.
SYNCDIV: u3 = 0x0,
reserved28: u1 = 0,
/// SYNC signal source selection These bits are set and cleared by software to select the SYNC signal source. Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the periodic USB SOF will not be generated by the host. No SYNC signal will therefore be provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs should be used as SYNC signal.
SYNCSRC: u2 = 0x2,
reserved31: u1 = 0,
/// SYNC polarity selection This bit is set and cleared by software to select the input polarity for the SYNC signal source.
SYNCPOL: u1 = 0x0,
}),
/// CRS interrupt and status register
/// offset: 0x08
ISR: mmio.Mmio(packed struct(u32) {
/// SYNC event OK flag This flag is set by hardware when the measured frequency error is smaller than FELIM * 3. This means that either no adjustment of the TRIM value is needed or that an adjustment by one trimming step is enough to compensate the frequency error. An interrupt is generated if the SYNCOKIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCOKC bit in the CRS_ICR register.
SYNCOKF: u1 = 0x0,
/// SYNC warning flag This flag is set by hardware when the measured frequency error is greater than or equal to FELIM * 3, but smaller than FELIM * 128. This means that to compensate the frequency error, the TRIM value must be adjusted by two steps or more. An interrupt is generated if the SYNCWARNIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCWARNC bit in the CRS_ICR register.
SYNCWARNF: u1 = 0x0,
/// Error flag This flag is set by hardware in case of any synchronization or trimming error. It is the logical OR of the TRIMOVF, SYNCMISS and SYNCERR bits. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software in reaction to setting the ERRC bit in the CRS_ICR register, which clears the TRIMOVF, SYNCMISS and SYNCERR bits.
ERRF: u1 = 0x0,
/// Expected SYNC flag This flag is set by hardware when the frequency error counter reached a zero value. An interrupt is generated if the ESYNCIE bit is set in the CRS_CR register. It is cleared by software by setting the ESYNCC bit in the CRS_ICR register.
ESYNCF: u1 = 0x0,
reserved8: u4 = 0,
/// SYNC error This flag is set by hardware when the SYNC pulse arrives before the ESYNC event and the measured frequency error is greater than or equal to FELIM * 128. This means that the frequency error is too big (internal frequency too low) to be compensated by adjusting the TRIM value, and that some other action should be taken. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register.
SYNCERR: u1 = 0x0,
/// SYNC missed This flag is set by hardware when the frequency error counter reached value FELIM * 128 and no SYNC was detected, meaning either that a SYNC pulse was missed or that the frequency error is too big (internal frequency too high) to be compensated by adjusting the TRIM value, and that some other action should be taken. At this point, the frequency error counter is stopped (waiting for a next SYNC) and an interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register.
SYNCMISS: u1 = 0x0,
/// Trimming overflow or underflow This flag is set by hardware when the automatic trimming tries to over- or under-flow the TRIM value. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register.
TRIMOVF: u1 = 0x0,
reserved15: u4 = 0,
/// Frequency error direction FEDIR is the counting direction of the frequency error counter latched in the time of the last SYNC event. It shows whether the actual frequency is below or above the target.
FEDIR: u1 = 0x0,
/// Frequency error capture FECAP is the frequency error counter value latched in the time ofthe last SYNC event. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details about FECAP usage.
FECAP: u16 = 0x0,
}),
/// CRS interrupt flag clear register
/// offset: 0x0c
ICR: mmio.Mmio(packed struct(u32) {
/// SYNC event OK clear flag Writing 1 to this bit clears the SYNCOKF flag in the CRS_ISR register.
SYNCOKC: u1 = 0x0,
/// SYNC warning clear flag Writing 1 to this bit clears the SYNCWARNF flag in the CRS_ISR register.
SYNCWARNC: u1 = 0x0,
/// Error clear flag Writing 1 to this bit clears TRIMOVF, SYNCMISS and SYNCERR bits and consequently also the ERRF flag in the CRS_ISR register.
ERRC: u1 = 0x0,
/// Expected SYNC clear flag Writing 1 to this bit clears the ESYNCF flag in the CRS_ISR register.
ESYNCC: u1 = 0x0,
padding: u28 = 0,
}),
};

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src/stm32g4/types/peripherals/DAC1.zig Normal file
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const microzig = @import("microzig");
const mmio = microzig.mmio;
const types = @import("../../types.zig");
/// Digital-to-analog converter
pub const DAC1 = extern struct {
/// DAC control register
/// offset: 0x00
DAC_CR: mmio.Mmio(packed struct(u32) {
/// DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1.
EN1: u1 = 0x0,
/// DAC channel1 trigger enable
TEN1: u1 = 0x0,
/// DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).
TSEL1: u4 = 0x0,
/// DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled).
WAVE1: u2 = 0x0,
/// DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095
MAMP1: u4 = 0x0,
/// DAC channel1 DMA enable This bit is set and cleared by software.
DMAEN1: u1 = 0x0,
/// DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software.
DMAUDRIE1: u1 = 0x0,
/// DAC Channel 1 calibration enable This bit is set and cleared by software to enable/disable DAC channel 1 calibration, it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored.
CEN1: u1 = 0x0,
reserved16: u1 = 0,
/// DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2.
EN2: u1 = 0x0,
/// DAC channel2 trigger enable
TEN2: u1 = 0x0,
/// DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled).
TSEL2: u4 = 0x0,
/// DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled)
WAVE2: u2 = 0x0,
/// DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095
MAMP2: u4 = 0x0,
/// DAC channel2 DMA enable This bit is set and cleared by software.
DMAEN2: u1 = 0x0,
/// DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software.
DMAUDRIE2: u1 = 0x0,
/// DAC Channel 2 calibration enable This bit is set and cleared by software to enable/disable DAC channel 2 calibration, it can be written only if bit EN2=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored.
CEN2: u1 = 0x0,
padding: u1 = 0,
}),
/// DAC software trigger register
/// offset: 0x04
DAC_SWTRGR: mmio.Mmio(packed struct(u32) {
/// DAC channel1 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR1 register value has been loaded into the DAC_DOR1 register.
SWTRIG1: u1 = 0x0,
/// DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2 register value has been loaded into the DAC_DOR2 register.
SWTRIG2: u1 = 0x0,
reserved16: u14 = 0,
/// DAC channel1 software trigger B
SWTRIGB1: u1 = 0x0,
/// DAC channel2 software trigger B
SWTRIGB2: u1 = 0x0,
padding: u14 = 0,
}),
/// DAC channel1 12-bit right-aligned data holding register
/// offset: 0x08
DAC_DHR12R1: mmio.Mmio(packed struct(u32) {
/// DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.
DACC1DHR: u12 = 0x0,
reserved16: u4 = 0,
/// DAC channel1 12-bit right-aligned data B
DACC1DHRB: u12 = 0x0,
padding: u4 = 0,
}),
/// DAC channel1 12-bit left aligned data holding register
/// offset: 0x0c
DAC_DHR12L1: mmio.Mmio(packed struct(u32) {
reserved4: u4 = 0,
/// DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.
DACC1DHR: u12 = 0x0,
reserved20: u4 = 0,
/// DAC channel1 12-bit left-aligned data B
DACC1DHRB: u12 = 0x0,
}),
/// DAC channel1 8-bit right aligned data holding register
/// offset: 0x10
DAC_DHR8R1: mmio.Mmio(packed struct(u32) {
/// DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1.
DACC1DHR: u8 = 0x0,
/// DAC channel1 8-bit right-aligned data
DACC1DHRB: u8 = 0x0,
padding: u16 = 0,
}),
/// DAC channel2 12-bit right aligned data holding register
/// offset: 0x14
DAC_DHR12R2: mmio.Mmio(packed struct(u32) {
/// DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.
DACC2DHR: u12 = 0x0,
reserved16: u4 = 0,
/// DAC channel2 12-bit right-aligned data
DACC2DHRB: u12 = 0x0,
padding: u4 = 0,
}),
/// DAC channel2 12-bit left aligned data holding register
/// offset: 0x18
DAC_DHR12L2: mmio.Mmio(packed struct(u32) {
reserved4: u4 = 0,
/// DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2.
DACC2DHR: u12 = 0x0,
reserved20: u4 = 0,
/// DAC channel2 12-bit left-aligned data B
DACC2DHRB: u12 = 0x0,
}),
/// DAC channel2 8-bit right-aligned data holding register
/// offset: 0x1c
DAC_DHR8R2: mmio.Mmio(packed struct(u32) {
/// DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2.
DACC2DHR: u8 = 0x0,
/// DAC channel2 8-bit right-aligned data
DACC2DHRB: u8 = 0x0,
padding: u16 = 0,
}),
/// Dual DAC 12-bit right-aligned data holding register
/// offset: 0x20
DAC_DHR12RD: mmio.Mmio(packed struct(u32) {
/// DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.
DACC1DHR: u12 = 0x0,
reserved16: u4 = 0,
/// DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.
DACC2DHR: u12 = 0x0,
padding: u4 = 0,
}),
/// DUAL DAC 12-bit left aligned data holding register
/// offset: 0x24
DAC_DHR12LD: mmio.Mmio(packed struct(u32) {
reserved4: u4 = 0,
/// DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1.
DACC1DHR: u12 = 0x0,
reserved20: u4 = 0,
/// DAC channel2 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel2.
DACC2DHR: u12 = 0x0,
}),
/// DUAL DAC 8-bit right aligned data holding register
/// offset: 0x28
DAC_DHR8RD: mmio.Mmio(packed struct(u32) {
/// DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1.
DACC1DHR: u8 = 0x0,
/// DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2.
DACC2DHR: u8 = 0x0,
padding: u16 = 0,
}),
/// DAC channel1 data output register
/// offset: 0x2c
DAC_DOR1: mmio.Mmio(packed struct(u32) {
/// DAC channel1 data output These bits are read-only, they contain data output for DAC channel1.
DACC1DOR: u12 = 0x0,
reserved16: u4 = 0,
/// DAC channel1 data output
DACC1DORB: u12 = 0x0,
padding: u4 = 0,
}),
/// DAC channel2 data output register
/// offset: 0x30
DAC_DOR2: mmio.Mmio(packed struct(u32) {
/// DAC channel2 data output These bits are read-only, they contain data output for DAC channel2.
DACC2DOR: u12 = 0x0,
reserved16: u4 = 0,
/// DAC channel2 data output
DACC2DORB: u12 = 0x0,
padding: u4 = 0,
}),
/// DAC status register
/// offset: 0x34
DAC_SR: mmio.Mmio(packed struct(u32) {
reserved11: u11 = 0,
/// DAC channel1 ready status bit
DAC1RDY: u1 = 0x0,
/// DAC channel1 output register status bit
DORSTAT1: u1 = 0x0,
/// DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1).
DMAUDR1: u1 = 0x0,
/// DAC Channel 1 calibration offset status This bit is set and cleared by hardware
CAL_FLAG1: u1 = 0x0,
/// DAC Channel 1 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete. (It takes about 3LSI periods of synchronization).
BWST1: u1 = 0x0,
reserved27: u11 = 0,
/// DAC channel 2 ready status bit
DAC2RDY: u1 = 0x0,
/// DAC channel 2 output register status bit
DORSTAT2: u1 = 0x0,
/// DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1).
DMAUDR2: u1 = 0x0,
/// DAC Channel 2 calibration offset status This bit is set and cleared by hardware
CAL_FLAG2: u1 = 0x0,
/// DAC Channel 2 busy writing sample time flag This bit is systematically set just after Sample & Hold mode enable and is set each time the software writes the register DAC_SHSR2, It is cleared by hardware when the write operation of DAC_SHSR2 is complete. (It takes about 3 LSI periods of synchronization).
BWST2: u1 = 0x0,
}),
/// DAC calibration control register
/// offset: 0x38
DAC_CCR: mmio.Mmio(packed struct(u32) {
/// DAC Channel 1 offset trimming value
OTRIM1: u5 = 0x0,
reserved16: u11 = 0,
/// DAC Channel 2 offset trimming value
OTRIM2: u5 = 0x0,
padding: u11 = 0,
}),
/// DAC mode control register
/// offset: 0x3c
DAC_MCR: mmio.Mmio(packed struct(u32) {
/// DAC Channel 1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1=0 and bit CEN1 =0 in the DAC_CR register). If EN1=1 or CEN1 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 1 mode: DAC Channel 1 in normal Mode DAC Channel 1 in sample &amp; hold mode
MODE1: u3 = 0x0,
reserved8: u5 = 0,
/// DAC Channel1 DMA double data mode
DMADOUBLE1: u1 = 0x0,
/// Enable signed format for DAC channel1
SINFORMAT1: u1 = 0x0,
reserved14: u4 = 0,
/// High frequency interface mode selection
HFSEL: u2 = 0x0,
/// DAC Channel 2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 2 mode: DAC Channel 2 in normal Mode DAC Channel 2 in sample &amp; hold mode
MODE2: u3 = 0x0,
reserved24: u5 = 0,
/// DAC Channel2 DMA double data mode
DMADOUBLE2: u1 = 0x0,
/// Enable signed format for DAC channel2
SINFORMAT2: u1 = 0x0,
padding: u6 = 0,
}),
/// DAC Sample and Hold sample time register 1
/// offset: 0x40
DAC_SHSR1: mmio.Mmio(packed struct(u32) {
/// DAC Channel 1 sample Time (only valid in sample &amp; hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored.
TSAMPLE1: u10 = 0x0,
padding: u22 = 0,
}),
/// DAC Sample and Hold sample time register 2
/// offset: 0x44
DAC_SHSR2: mmio.Mmio(packed struct(u32) {
/// DAC Channel 2 sample Time (only valid in sample &amp; hold mode) These bits can be written when the DAC channel2 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, if BWSTx=1, the write operation is ignored.
TSAMPLE2: u10 = 0x0,
padding: u22 = 0,
}),
/// DAC Sample and Hold hold time register
/// offset: 0x48
DAC_SHHR: mmio.Mmio(packed struct(u32) {
/// DAC Channel 1 hold Time (only valid in sample &amp; hold mode) Hold time= (THOLD[9:0]) x T LSI
THOLD1: u10 = 0x1,
reserved16: u6 = 0,
/// DAC Channel 2 hold time (only valid in sample &amp; hold mode). Hold time= (THOLD[9:0]) x T LSI
THOLD2: u10 = 0x1,
padding: u6 = 0,
}),
/// DAC Sample and Hold refresh time register
/// offset: 0x4c
DAC_SHRR: mmio.Mmio(packed struct(u32) {
/// DAC Channel 1 refresh Time (only valid in sample &amp; hold mode) Refresh time= (TREFRESH[7:0]) x T LSI
TREFRESH1: u8 = 0x1,
reserved16: u8 = 0,
/// DAC Channel 2 refresh Time (only valid in sample &amp; hold mode) Refresh time= (TREFRESH[7:0]) x T LSI
TREFRESH2: u8 = 0x1,
padding: u8 = 0,
}),
/// offset: 0x50
reserved80: [8]u8,
/// Sawtooth register
/// offset: 0x58
DAC_STR1: mmio.Mmio(packed struct(u32) {
/// DAC Channel 1 Sawtooth reset value
STRSTDATA1: u12 = 0x0,
/// DAC Channel1 Sawtooth direction setting
STDIR1: u1 = 0x0,
reserved16: u3 = 0,
/// DAC CH1 Sawtooth increment value (12.4 bit format)
STINCDATA1: u16 = 0x0,
}),
/// Sawtooth register
/// offset: 0x5c
DAC_STR2: mmio.Mmio(packed struct(u32) {
/// DAC Channel 2 Sawtooth reset value
STRSTDATA2: u12 = 0x0,
/// DAC Channel2 Sawtooth direction setting
STDIR2: u1 = 0x0,
reserved16: u3 = 0,
/// DAC CH2 Sawtooth increment value (12.4 bit format)
STINCDATA2: u16 = 0x0,
}),
/// Sawtooth Mode register
/// offset: 0x60
DAC_STMODR: mmio.Mmio(packed struct(u32) {
/// DAC Channel 1 Sawtooth Reset trigger selection
STRSTTRIGSEL1: u4 = 0x0,
reserved8: u4 = 0,
/// DAC Channel 1 Sawtooth Increment trigger selection
STINCTRIGSEL1: u4 = 0x0,
reserved16: u4 = 0,
/// DAC Channel 1 Sawtooth Reset trigger selection
STRSTTRIGSEL2: u4 = 0x0,
reserved24: u4 = 0,
/// DAC Channel 2 Sawtooth Increment trigger selection
STINCTRIGSEL2: u4 = 0x0,
padding: u4 = 0,
}),
};

103
src/stm32g4/types/peripherals/DBGMCU.zig Normal file
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const microzig = @import("microzig");
const mmio = microzig.mmio;
const types = @import("../../types.zig");
/// Debug support
pub const DBGMCU = extern struct {
/// MCU Device ID Code Register
/// offset: 0x00
IDCODE: mmio.Mmio(packed struct(u32) {
/// Device Identifier
DEV_ID: u16 = 0x0,
/// Revision Identifier
REV_ID: u16 = 0x0,
}),
/// Debug MCU Configuration Register
/// offset: 0x04
CR: mmio.Mmio(packed struct(u32) {
/// Debug Sleep Mode
DBG_SLEEP: u1 = 0x0,
/// Debug Stop Mode
DBG_STOP: u1 = 0x0,
/// Debug Standby Mode
DBG_STANDBY: u1 = 0x0,
reserved5: u2 = 0,
/// Trace pin assignment control
TRACE_IOEN: u1 = 0x0,
/// Trace pin assignment control
TRACE_MODE: u2 = 0x0,
padding: u24 = 0,
}),
/// APB Low Freeze Register 1
/// offset: 0x08
APB1L_FZ: mmio.Mmio(packed struct(u32) {
/// Debug Timer 2 stopped when Core is halted
DBG_TIMER2_STOP: u1 = 0x0,
/// TIM3 counter stopped when core is halted
DBG_TIM3_STOP: u1 = 0x0,
/// TIM4 counter stopped when core is halted
DBG_TIM4_STOP: u1 = 0x0,
/// TIM5 counter stopped when core is halted
DBG_TIM5_STOP: u1 = 0x0,
/// Debug Timer 6 stopped when Core is halted
DBG_TIMER6_STOP: u1 = 0x0,
/// TIM7 counter stopped when core is halted
DBG_TIM7_STOP: u1 = 0x0,
reserved10: u4 = 0,
/// Debug RTC stopped when Core is halted
DBG_RTC_STOP: u1 = 0x0,
/// Debug Window Wachdog stopped when Core is halted
DBG_WWDG_STOP: u1 = 0x0,
/// Debug Independent Wachdog stopped when Core is halted
DBG_IWDG_STOP: u1 = 0x0,
reserved21: u8 = 0,
/// I2C1 SMBUS timeout mode stopped when core is halted
DBG_I2C1_STOP: u1 = 0x0,
/// I2C2 SMBUS timeout mode stopped when core is halted
DBG_I2C2_STOP: u1 = 0x0,
reserved30: u7 = 0,
/// I2C3 SMBUS timeout mode stopped when core is halted
DBG_I2C3_STOP: u1 = 0x0,
/// LPTIM1 counter stopped when core is halted
DBG_LPTIMER_STOP: u1 = 0x0,
}),
/// APB Low Freeze Register 2
/// offset: 0x0c
APB1H_FZ: mmio.Mmio(packed struct(u32) {
reserved1: u1 = 0,
/// DBG_I2C4_STOP
DBG_I2C4_STOP: u1 = 0x0,
padding: u30 = 0,
}),
/// APB High Freeze Register
/// offset: 0x10
APB2_FZ: mmio.Mmio(packed struct(u32) {
reserved11: u11 = 0,
/// TIM1 counter stopped when core is halted
DBG_TIM1_STOP: u1 = 0x0,
reserved13: u1 = 0,
/// TIM8 counter stopped when core is halted
DBG_TIM8_STOP: u1 = 0x0,
reserved16: u2 = 0,
/// TIM15 counter stopped when core is halted
DBG_TIM15_STOP: u1 = 0x0,
/// TIM16 counter stopped when core is halted
DBG_TIM16_STOP: u1 = 0x0,
/// TIM17 counter stopped when core is halted
DBG_TIM17_STOP: u1 = 0x0,
reserved20: u1 = 0,
/// TIM20counter stopped when core is halted
DBG_TIM20_STOP: u1 = 0x0,
reserved26: u5 = 0,
/// DBG_HRTIM0_STOP
DBG_HRTIM0_STOP: u1 = 0x0,
/// DBG_HRTIM0_STOP
DBG_HRTIM1_STOP: u1 = 0x0,
/// DBG_HRTIM0_STOP
DBG_HRTIM2_STOP: u1 = 0x0,
/// DBG_HRTIM0_STOP
DBG_HRTIM3_STOP: u1 = 0x0,
padding: u2 = 0,
}),
};

542
src/stm32g4/types/peripherals/DMA1.zig Normal file
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const microzig = @import("microzig");
const mmio = microzig.mmio;
const types = @import("../../types.zig");
/// DMA controller
pub const DMA1 = extern struct {
/// interrupt status register
/// offset: 0x00
ISR: mmio.Mmio(packed struct(u32) {
/// GIF1
GIF1: u1 = 0x0,
/// TCIF1
TCIF1: u1 = 0x0,
/// HTIF1
HTIF1: u1 = 0x0,
/// TEIF1
TEIF1: u1 = 0x0,
/// GIF2
GIF2: u1 = 0x0,
/// TCIF2
TCIF2: u1 = 0x0,
/// HTIF2
HTIF2: u1 = 0x0,
/// TEIF2
TEIF2: u1 = 0x0,
/// GIF3
GIF3: u1 = 0x0,
/// TCIF3
TCIF3: u1 = 0x0,
/// HTIF3
HTIF3: u1 = 0x0,
/// TEIF3
TEIF3: u1 = 0x0,
/// GIF4
GIF4: u1 = 0x0,
/// TCIF4
TCIF4: u1 = 0x0,
/// HTIF4
HTIF4: u1 = 0x0,
/// TEIF4
TEIF4: u1 = 0x0,
/// GIF5
GIF5: u1 = 0x0,
/// TCIF5
TCIF5: u1 = 0x0,
/// HTIF5
HTIF5: u1 = 0x0,
/// TEIF5
TEIF5: u1 = 0x0,
/// GIF6
GIF6: u1 = 0x0,
/// TCIF6
TCIF6: u1 = 0x0,
/// HTIF6
HTIF6: u1 = 0x0,
/// TEIF6
TEIF6: u1 = 0x0,
/// GIF7
GIF7: u1 = 0x0,
/// TCIF7
TCIF7: u1 = 0x0,
/// HTIF7
HTIF7: u1 = 0x0,
/// TEIF7
TEIF7: u1 = 0x0,
/// GIF8
GIF8: u1 = 0x0,
/// TCIF8
TCIF8: u1 = 0x0,
/// HTIF8
HTIF8: u1 = 0x0,
/// TEIF8
TEIF8: u1 = 0x0,
}),
/// DMA interrupt flag clear register
/// offset: 0x04
IFCR: mmio.Mmio(packed struct(u32) {
/// GIF1
GIF1: u1 = 0x0,
/// TCIF1
TCIF1: u1 = 0x0,
/// HTIF1
HTIF1: u1 = 0x0,
/// TEIF1
TEIF1: u1 = 0x0,
/// GIF2
GIF2: u1 = 0x0,
/// TCIF2
TCIF2: u1 = 0x0,
/// HTIF2
HTIF2: u1 = 0x0,
/// TEIF2
TEIF2: u1 = 0x0,
/// GIF3
GIF3: u1 = 0x0,
/// TCIF3
TCIF3: u1 = 0x0,
/// HTIF3
HTIF3: u1 = 0x0,
/// TEIF3
TEIF3: u1 = 0x0,
/// GIF4
GIF4: u1 = 0x0,
/// TCIF4
TCIF4: u1 = 0x0,
/// HTIF4
HTIF4: u1 = 0x0,
/// TEIF4
TEIF4: u1 = 0x0,
/// GIF5
GIF5: u1 = 0x0,
/// TCIF5
TCIF5: u1 = 0x0,
/// HTIF5
HTIF5: u1 = 0x0,
/// TEIF5
TEIF5: u1 = 0x0,
/// GIF6
GIF6: u1 = 0x0,
/// TCIF6
TCIF6: u1 = 0x0,
/// HTIF6
HTIF6: u1 = 0x0,
/// TEIF6
TEIF6: u1 = 0x0,
/// GIF7
GIF7: u1 = 0x0,
/// TCIF7
TCIF7: u1 = 0x0,
/// HTIF7
HTIF7: u1 = 0x0,
/// TEIF7
TEIF7: u1 = 0x0,
/// GIF8
GIF8: u1 = 0x0,
/// TCIF8
TCIF8: u1 = 0x0,
/// HTIF8
HTIF8: u1 = 0x0,
/// TEIF8
TEIF8: u1 = 0x0,
}),
/// DMA channel 1 configuration register
/// offset: 0x08
CCR1: mmio.Mmio(packed struct(u32) {
/// channel enable
EN: u1 = 0x0,
/// TCIE
TCIE: u1 = 0x0,
/// HTIE
HTIE: u1 = 0x0,
/// TEIE
TEIE: u1 = 0x0,
/// DIR
DIR: u1 = 0x0,
/// CIRC
CIRC: u1 = 0x0,
/// PINC
PINC: u1 = 0x0,
/// MINC
MINC: u1 = 0x0,
/// PSIZE
PSIZE: u2 = 0x0,
/// MSIZE
MSIZE: u2 = 0x0,
/// PL
PL: u2 = 0x0,
/// MEM2MEM
MEM2MEM: u1 = 0x0,
padding: u17 = 0,
}),
/// channel x number of data to transfer register
/// offset: 0x0c
CNDTR1: mmio.Mmio(packed struct(u32) {
/// Number of data items to transfer
NDT: u16 = 0x0,
padding: u16 = 0,
}),
/// DMA channel x peripheral address register
/// offset: 0x10
CPAR1: mmio.Mmio(packed struct(u32) {
/// Peripheral address
PA: u32 = 0x0,
}),
/// DMA channel x memory address register
/// offset: 0x14
CMAR1: mmio.Mmio(packed struct(u32) {
/// Memory 1 address (used in case of Double buffer mode)
MA: u32 = 0x0,
}),
/// offset: 0x18
reserved24: [4]u8,
/// DMA channel 2 configuration register
/// offset: 0x1c
CCR2: mmio.Mmio(packed struct(u32) {
/// channel enable
EN: u1 = 0x0,
/// TCIE
TCIE: u1 = 0x0,
/// HTIE
HTIE: u1 = 0x0,
/// TEIE
TEIE: u1 = 0x0,
/// DIR
DIR: u1 = 0x0,
/// CIRC
CIRC: u1 = 0x0,
/// PINC
PINC: u1 = 0x0,
/// MINC
MINC: u1 = 0x0,
/// PSIZE
PSIZE: u2 = 0x0,
/// MSIZE
MSIZE: u2 = 0x0,
/// PL
PL: u2 = 0x0,
/// MEM2MEM
MEM2MEM: u1 = 0x0,
padding: u17 = 0,
}),
/// channel x number of data to transfer register
/// offset: 0x20
CNDTR2: mmio.Mmio(packed struct(u32) {
/// Number of data items to transfer
NDT: u16 = 0x0,
padding: u16 = 0,
}),
/// DMA channel x peripheral address register
/// offset: 0x24
CPAR2: mmio.Mmio(packed struct(u32) {
/// Peripheral address
PA: u32 = 0x0,
}),
/// DMA channel x memory address register
/// offset: 0x28
CMAR2: mmio.Mmio(packed struct(u32) {
/// Memory 1 address (used in case of Double buffer mode)
MA: u32 = 0x0,
}),
/// offset: 0x2c
reserved44: [4]u8,
/// DMA channel 3 configuration register
/// offset: 0x30
CCR3: mmio.Mmio(packed struct(u32) {
/// channel enable
EN: u1 = 0x0,
/// TCIE
TCIE: u1 = 0x0,
/// HTIE
HTIE: u1 = 0x0,
/// TEIE
TEIE: u1 = 0x0,
/// DIR
DIR: u1 = 0x0,
/// CIRC
CIRC: u1 = 0x0,
/// PINC
PINC: u1 = 0x0,
/// MINC
MINC: u1 = 0x0,
/// PSIZE
PSIZE: u2 = 0x0,
/// MSIZE
MSIZE: u2 = 0x0,
/// PL
PL: u2 = 0x0,
/// MEM2MEM
MEM2MEM: u1 = 0x0,
padding: u17 = 0,
}),
/// channel x number of data to transfer register
/// offset: 0x34
CNDTR3: mmio.Mmio(packed struct(u32) {
/// Number of data items to transfer
NDT: u16 = 0x0,
padding: u16 = 0,
}),
/// DMA channel x peripheral address register
/// offset: 0x38
CPAR3: mmio.Mmio(packed struct(u32) {
/// Peripheral address
PA: u32 = 0x0,
}),
/// DMA channel x memory address register
/// offset: 0x3c
CMAR3: mmio.Mmio(packed struct(u32) {
/// Memory 1 address (used in case of Double buffer mode)
MA: u32 = 0x0,
}),
/// offset: 0x40
reserved64: [4]u8,
/// DMA channel 3 configuration register
/// offset: 0x44
CCR4: mmio.Mmio(packed struct(u32) {
/// channel enable
EN: u1 = 0x0,
/// TCIE
TCIE: u1 = 0x0,
/// HTIE
HTIE: u1 = 0x0,
/// TEIE
TEIE: u1 = 0x0,
/// DIR
DIR: u1 = 0x0,
/// CIRC
CIRC: u1 = 0x0,
/// PINC
PINC: u1 = 0x0,
/// MINC
MINC: u1 = 0x0,
/// PSIZE
PSIZE: u2 = 0x0,
/// MSIZE
MSIZE: u2 = 0x0,
/// PL
PL: u2 = 0x0,
/// MEM2MEM
MEM2MEM: u1 = 0x0,
padding: u17 = 0,
}),
/// channel x number of data to transfer register
/// offset: 0x48
CNDTR4: mmio.Mmio(packed struct(u32) {
/// Number of data items to transfer
NDT: u16 = 0x0,
padding: u16 = 0,
}),
/// DMA channel x peripheral address register
/// offset: 0x4c
CPAR4: mmio.Mmio(packed struct(u32) {
/// Peripheral address
PA: u32 = 0x0,
}),
/// DMA channel x memory address register
/// offset: 0x50
CMAR4: mmio.Mmio(packed struct(u32) {
/// Memory 1 address (used in case of Double buffer mode)
MA: u32 = 0x0,
}),
/// offset: 0x54
reserved84: [4]u8,
/// DMA channel 4 configuration register
/// offset: 0x58
CCR5: mmio.Mmio(packed struct(u32) {
/// channel enable
EN: u1 = 0x0,
/// TCIE
TCIE: u1 = 0x0,
/// HTIE
HTIE: u1 = 0x0,
/// TEIE
TEIE: u1 = 0x0,
/// DIR
DIR: u1 = 0x0,
/// CIRC
CIRC: u1 = 0x0,
/// PINC
PINC: u1 = 0x0,
/// MINC
MINC: u1 = 0x0,
/// PSIZE
PSIZE: u2 = 0x0,
/// MSIZE
MSIZE: u2 = 0x0,
/// PL
PL: u2 = 0x0,
/// MEM2MEM
MEM2MEM: u1 = 0x0,
padding: u17 = 0,
}),
/// channel x number of data to transfer register
/// offset: 0x5c
CNDTR5: mmio.Mmio(packed struct(u32) {
/// Number of data items to transfer
NDT: u16 = 0x0,
padding: u16 = 0,
}),
/// DMA channel x peripheral address register
/// offset: 0x60
CPAR5: mmio.Mmio(packed struct(u32) {
/// Peripheral address
PA: u32 = 0x0,
}),
/// DMA channel x memory address register
/// offset: 0x64
CMAR5: mmio.Mmio(packed struct(u32) {
/// Memory 1 address (used in case of Double buffer mode)
MA: u32 = 0x0,
}),
/// offset: 0x68
reserved104: [4]u8,
/// DMA channel 5 configuration register
/// offset: 0x6c
CCR6: mmio.Mmio(packed struct(u32) {
/// channel enable
EN: u1 = 0x0,
/// TCIE
TCIE: u1 = 0x0,
/// HTIE
HTIE: u1 = 0x0,
/// TEIE
TEIE: u1 = 0x0,
/// DIR
DIR: u1 = 0x0,
/// CIRC
CIRC: u1 = 0x0,
/// PINC
PINC: u1 = 0x0,
/// MINC
MINC: u1 = 0x0,
/// PSIZE
PSIZE: u2 = 0x0,
/// MSIZE
MSIZE: u2 = 0x0,
/// PL
PL: u2 = 0x0,
/// MEM2MEM
MEM2MEM: u1 = 0x0,
padding: u17 = 0,
}),
/// channel x number of data to transfer register
/// offset: 0x70
CNDTR6: mmio.Mmio(packed struct(u32) {
/// Number of data items to transfer
NDT: u16 = 0x0,
padding: u16 = 0,
}),
/// DMA channel x peripheral address register
/// offset: 0x74
CPAR6: mmio.Mmio(packed struct(u32) {
/// Peripheral address
PA: u32 = 0x0,
}),
/// DMA channel x memory address register
/// offset: 0x78
CMAR6: mmio.Mmio(packed struct(u32) {
/// Memory 1 address (used in case of Double buffer mode)
MA: u32 = 0x0,
}),
/// offset: 0x7c
reserved124: [4]u8,
/// DMA channel 6 configuration register
/// offset: 0x80
CCR7: mmio.Mmio(packed struct(u32) {
/// channel enable
EN: u1 = 0x0,
/// TCIE
TCIE: u1 = 0x0,
/// HTIE
HTIE: u1 = 0x0,
/// TEIE
TEIE: u1 = 0x0,
/// DIR
DIR: u1 = 0x0,
/// CIRC
CIRC: u1 = 0x0,
/// PINC
PINC: u1 = 0x0,
/// MINC
MINC: u1 = 0x0,
/// PSIZE
PSIZE: u2 = 0x0,
/// MSIZE
MSIZE: u2 = 0x0,
/// PL
PL: u2 = 0x0,
/// MEM2MEM
MEM2MEM: u1 = 0x0,
padding: u17 = 0,
}),
/// channel x number of data to transfer register
/// offset: 0x84
CNDTR7: mmio.Mmio(packed struct(u32) {
/// Number of data items to transfer
NDT: u16 = 0x0,
padding: u16 = 0,
}),
/// DMA channel x peripheral address register
/// offset: 0x88
CPAR7: mmio.Mmio(packed struct(u32) {
/// Peripheral address
PA: u32 = 0x0,
}),
/// DMA channel x memory address register
/// offset: 0x8c
CMAR7: mmio.Mmio(packed struct(u32) {
/// Memory 1 address (used in case of Double buffer mode)
MA: u32 = 0x0,
}),
/// offset: 0x90
reserved144: [4]u8,
/// DMA channel 7 configuration register
/// offset: 0x94
CCR8: mmio.Mmio(packed struct(u32) {
/// channel enable
EN: u1 = 0x0,
/// TCIE
TCIE: u1 = 0x0,
/// HTIE
HTIE: u1 = 0x0,
/// TEIE
TEIE: u1 = 0x0,
/// DIR
DIR: u1 = 0x0,
/// CIRC
CIRC: u1 = 0x0,
/// PINC
PINC: u1 = 0x0,
/// MINC
MINC: u1 = 0x0,
/// PSIZE
PSIZE: u2 = 0x0,
/// MSIZE
MSIZE: u2 = 0x0,
/// PL
PL: u2 = 0x0,
/// MEM2MEM
MEM2MEM: u1 = 0x0,
padding: u17 = 0,
}),
/// channel x number of data to transfer register
/// offset: 0x98
CNDTR8: mmio.Mmio(packed struct(u32) {
/// Number of data items to transfer
NDT: u16 = 0x0,
padding: u16 = 0,
}),
/// DMA channel x peripheral address register
/// offset: 0x9c
CPAR8: mmio.Mmio(packed struct(u32) {
/// Peripheral address
PA: u32 = 0x0,
}),
/// DMA channel x memory address register
/// offset: 0xa0
CMAR8: mmio.Mmio(packed struct(u32) {
/// Memory 1 address (used in case of Double buffer mode)
MA: u32 = 0x0,
}),
};

446
src/stm32g4/types/peripherals/DMAMUX.zig Normal file
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const microzig = @import("microzig");
const mmio = microzig.mmio;
const types = @import("../../types.zig");
/// DMAMUX
pub const DMAMUX = extern struct {
/// DMAMux - DMA request line multiplexer channel x control register
/// offset: 0x00
C0CR: mmio.Mmio(packed struct(u32) {
/// Input DMA request line selected
DMAREQ_ID: u7 = 0x0,
reserved8: u1 = 0,
/// Interrupt enable at synchronization event overrun
SOIE: u1 = 0x0,
/// Event generation enable/disable
EGE: u1 = 0x0,
reserved16: u6 = 0,
/// Synchronous operating mode enable/disable
SE: u1 = 0x0,
/// Synchronization event type selector Defines the synchronization event on the selected synchronization input:
SPOL: u2 = 0x0,
/// Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
NBREQ: u5 = 0x0,
/// Synchronization input selected
SYNC_ID: u5 = 0x0,
padding: u3 = 0,
}),
/// DMAMux - DMA request line multiplexer channel x control register
/// offset: 0x04
C1CR: mmio.Mmio(packed struct(u32) {
/// Input DMA request line selected
DMAREQ_ID: u7 = 0x0,
reserved8: u1 = 0,
/// Interrupt enable at synchronization event overrun
SOIE: u1 = 0x0,
/// Event generation enable/disable
EGE: u1 = 0x0,
reserved16: u6 = 0,
/// Synchronous operating mode enable/disable
SE: u1 = 0x0,
/// Synchronization event type selector Defines the synchronization event on the selected synchronization input:
SPOL: u2 = 0x0,
/// Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
NBREQ: u5 = 0x0,
/// Synchronization input selected
SYNC_ID: u5 = 0x0,
padding: u3 = 0,
}),
/// DMAMux - DMA request line multiplexer channel x control register
/// offset: 0x08
C2CR: mmio.Mmio(packed struct(u32) {
/// Input DMA request line selected
DMAREQ_ID: u7 = 0x0,
reserved8: u1 = 0,
/// Interrupt enable at synchronization event overrun
SOIE: u1 = 0x0,
/// Event generation enable/disable
EGE: u1 = 0x0,
reserved16: u6 = 0,
/// Synchronous operating mode enable/disable
SE: u1 = 0x0,
/// Synchronization event type selector Defines the synchronization event on the selected synchronization input:
SPOL: u2 = 0x0,
/// Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
NBREQ: u5 = 0x0,
/// Synchronization input selected
SYNC_ID: u5 = 0x0,
padding: u3 = 0,
}),
/// DMAMux - DMA request line multiplexer channel x control register
/// offset: 0x0c
C3CR: mmio.Mmio(packed struct(u32) {
/// Input DMA request line selected
DMAREQ_ID: u7 = 0x0,
reserved8: u1 = 0,
/// Interrupt enable at synchronization event overrun
SOIE: u1 = 0x0,
/// Event generation enable/disable
EGE: u1 = 0x0,
reserved16: u6 = 0,
/// Synchronous operating mode enable/disable
SE: u1 = 0x0,
/// Synchronization event type selector Defines the synchronization event on the selected synchronization input:
SPOL: u2 = 0x0,
/// Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
NBREQ: u5 = 0x0,
/// Synchronization input selected
SYNC_ID: u5 = 0x0,
padding: u3 = 0,
}),
/// DMAMux - DMA request line multiplexer channel x control register
/// offset: 0x10
C4CR: mmio.Mmio(packed struct(u32) {
/// Input DMA request line selected
DMAREQ_ID: u7 = 0x0,
reserved8: u1 = 0,
/// Interrupt enable at synchronization event overrun
SOIE: u1 = 0x0,
/// Event generation enable/disable
EGE: u1 = 0x0,
reserved16: u6 = 0,
/// Synchronous operating mode enable/disable
SE: u1 = 0x0,
/// Synchronization event type selector Defines the synchronization event on the selected synchronization input:
SPOL: u2 = 0x0,
/// Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
NBREQ: u5 = 0x0,
/// Synchronization input selected
SYNC_ID: u5 = 0x0,
padding: u3 = 0,
}),
/// DMAMux - DMA request line multiplexer channel x control register
/// offset: 0x14
C5CR: mmio.Mmio(packed struct(u32) {
/// Input DMA request line selected
DMAREQ_ID: u7 = 0x0,
reserved8: u1 = 0,
/// Interrupt enable at synchronization event overrun
SOIE: u1 = 0x0,
/// Event generation enable/disable
EGE: u1 = 0x0,
reserved16: u6 = 0,
/// Synchronous operating mode enable/disable
SE: u1 = 0x0,
/// Synchronization event type selector Defines the synchronization event on the selected synchronization input:
SPOL: u2 = 0x0,
/// Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
NBREQ: u5 = 0x0,
/// Synchronization input selected
SYNC_ID: u5 = 0x0,
padding: u3 = 0,
}),
/// DMAMux - DMA request line multiplexer channel x control register
/// offset: 0x18
C6CR: mmio.Mmio(packed struct(u32) {
/// Input DMA request line selected
DMAREQ_ID: u7 = 0x0,
reserved8: u1 = 0,
/// Interrupt enable at synchronization event overrun
SOIE: u1 = 0x0,
/// Event generation enable/disable
EGE: u1 = 0x0,
reserved16: u6 = 0,
/// Synchronous operating mode enable/disable
SE: u1 = 0x0,
/// Synchronization event type selector Defines the synchronization event on the selected synchronization input:
SPOL: u2 = 0x0,
/// Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
NBREQ: u5 = 0x0,
/// Synchronization input selected
SYNC_ID: u5 = 0x0,
padding: u3 = 0,
}),
/// DMAMux - DMA request line multiplexer channel x control register
/// offset: 0x1c
C7CR: mmio.Mmio(packed struct(u32) {
/// Input DMA request line selected
DMAREQ_ID: u7 = 0x0,
reserved8: u1 = 0,
/// Interrupt enable at synchronization event overrun
SOIE: u1 = 0x0,
/// Event generation enable/disable
EGE: u1 = 0x0,
reserved16: u6 = 0,
/// Synchronous operating mode enable/disable
SE: u1 = 0x0,
/// Synchronization event type selector Defines the synchronization event on the selected synchronization input:
SPOL: u2 = 0x0,
/// Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
NBREQ: u5 = 0x0,
/// Synchronization input selected
SYNC_ID: u5 = 0x0,
padding: u3 = 0,
}),
/// DMAMux - DMA request line multiplexer channel x control register
/// offset: 0x20
C8CR: mmio.Mmio(packed struct(u32) {
/// Input DMA request line selected
DMAREQ_ID: u7 = 0x0,
reserved8: u1 = 0,
/// Interrupt enable at synchronization event overrun
SOIE: u1 = 0x0,
/// Event generation enable/disable
EGE: u1 = 0x0,
reserved16: u6 = 0,
/// Synchronous operating mode enable/disable
SE: u1 = 0x0,
/// Synchronization event type selector Defines the synchronization event on the selected synchronization input:
SPOL: u2 = 0x0,
/// Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
NBREQ: u5 = 0x0,
/// Synchronization input selected
SYNC_ID: u5 = 0x0,
padding: u3 = 0,
}),
/// DMAMux - DMA request line multiplexer channel x control register
/// offset: 0x24
C9CR: mmio.Mmio(packed struct(u32) {
/// Input DMA request line selected
DMAREQ_ID: u7 = 0x0,
reserved8: u1 = 0,
/// Interrupt enable at synchronization event overrun
SOIE: u1 = 0x0,
/// Event generation enable/disable
EGE: u1 = 0x0,
reserved16: u6 = 0,
/// Synchronous operating mode enable/disable
SE: u1 = 0x0,
/// Synchronization event type selector Defines the synchronization event on the selected synchronization input:
SPOL: u2 = 0x0,
/// Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
NBREQ: u5 = 0x0,
/// Synchronization input selected
SYNC_ID: u5 = 0x0,
padding: u3 = 0,
}),
/// DMAMux - DMA request line multiplexer channel x control register
/// offset: 0x28
C10CR: mmio.Mmio(packed struct(u32) {
/// Input DMA request line selected
DMAREQ_ID: u7 = 0x0,
reserved8: u1 = 0,
/// Interrupt enable at synchronization event overrun
SOIE: u1 = 0x0,
/// Event generation enable/disable
EGE: u1 = 0x0,
reserved16: u6 = 0,
/// Synchronous operating mode enable/disable
SE: u1 = 0x0,
/// Synchronization event type selector Defines the synchronization event on the selected synchronization input:
SPOL: u2 = 0x0,
/// Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
NBREQ: u5 = 0x0,
/// Synchronization input selected
SYNC_ID: u5 = 0x0,
padding: u3 = 0,
}),
/// DMAMux - DMA request line multiplexer channel x control register
/// offset: 0x2c
C11CR: mmio.Mmio(packed struct(u32) {
/// Input DMA request line selected
DMAREQ_ID: u7 = 0x0,
reserved8: u1 = 0,
/// Interrupt enable at synchronization event overrun
SOIE: u1 = 0x0,
/// Event generation enable/disable
EGE: u1 = 0x0,
reserved16: u6 = 0,
/// Synchronous operating mode enable/disable
SE: u1 = 0x0,
/// Synchronization event type selector Defines the synchronization event on the selected synchronization input:
SPOL: u2 = 0x0,
/// Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
NBREQ: u5 = 0x0,
/// Synchronization input selected
SYNC_ID: u5 = 0x0,
padding: u3 = 0,
}),
/// DMAMux - DMA request line multiplexer channel x control register
/// offset: 0x30
C12CR: mmio.Mmio(packed struct(u32) {
/// Input DMA request line selected
DMAREQ_ID: u7 = 0x0,
reserved8: u1 = 0,
/// Interrupt enable at synchronization event overrun
SOIE: u1 = 0x0,
/// Event generation enable/disable
EGE: u1 = 0x0,
reserved16: u6 = 0,
/// Synchronous operating mode enable/disable
SE: u1 = 0x0,
/// Synchronization event type selector Defines the synchronization event on the selected synchronization input:
SPOL: u2 = 0x0,
/// Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
NBREQ: u5 = 0x0,
/// Synchronization input selected
SYNC_ID: u5 = 0x0,
padding: u3 = 0,
}),
/// DMAMux - DMA request line multiplexer channel x control register
/// offset: 0x34
C13CR: mmio.Mmio(packed struct(u32) {
/// Input DMA request line selected
DMAREQ_ID: u7 = 0x0,
reserved8: u1 = 0,
/// Interrupt enable at synchronization event overrun
SOIE: u1 = 0x0,
/// Event generation enable/disable
EGE: u1 = 0x0,
reserved16: u6 = 0,
/// Synchronous operating mode enable/disable
SE: u1 = 0x0,
/// Synchronization event type selector Defines the synchronization event on the selected synchronization input:
SPOL: u2 = 0x0,
/// Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
NBREQ: u5 = 0x0,
/// Synchronization input selected
SYNC_ID: u5 = 0x0,
padding: u3 = 0,
}),
/// DMAMux - DMA request line multiplexer channel x control register
/// offset: 0x38
C14CR: mmio.Mmio(packed struct(u32) {
/// Input DMA request line selected
DMAREQ_ID: u7 = 0x0,
reserved8: u1 = 0,
/// Interrupt enable at synchronization event overrun
SOIE: u1 = 0x0,
/// Event generation enable/disable
EGE: u1 = 0x0,
reserved16: u6 = 0,
/// Synchronous operating mode enable/disable
SE: u1 = 0x0,
/// Synchronization event type selector Defines the synchronization event on the selected synchronization input:
SPOL: u2 = 0x0,
/// Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
NBREQ: u5 = 0x0,
/// Synchronization input selected
SYNC_ID: u5 = 0x0,
padding: u3 = 0,
}),
/// DMAMux - DMA request line multiplexer channel x control register
/// offset: 0x3c
C15CR: mmio.Mmio(packed struct(u32) {
/// Input DMA request line selected
DMAREQ_ID: u7 = 0x0,
reserved8: u1 = 0,
/// Interrupt enable at synchronization event overrun
SOIE: u1 = 0x0,
/// Event generation enable/disable
EGE: u1 = 0x0,
reserved16: u6 = 0,
/// Synchronous operating mode enable/disable
SE: u1 = 0x0,
/// Synchronization event type selector Defines the synchronization event on the selected synchronization input:
SPOL: u2 = 0x0,
/// Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset.
NBREQ: u5 = 0x0,
/// Synchronization input selected
SYNC_ID: u5 = 0x0,
padding: u3 = 0,
}),
/// offset: 0x40
reserved64: [64]u8,
/// DMAMUX request line multiplexer interrupt channel status register
/// offset: 0x80
CSR: mmio.Mmio(packed struct(u32) {
/// Synchronization overrun event flag
SOF: u16 = 0x0,
padding: u16 = 0,
}),
/// DMAMUX request line multiplexer interrupt clear flag register
/// offset: 0x84
CFR: mmio.Mmio(packed struct(u32) {
/// Clear synchronization overrun event flag
CSOF: u16 = 0x0,
padding: u16 = 0,
}),
/// offset: 0x88
reserved136: [120]u8,
/// DMAMux - DMA request generator channel x control register
/// offset: 0x100
RG0CR: mmio.Mmio(packed struct(u32) {
/// DMA request trigger input selected
SIG_ID: u5 = 0x0,
reserved8: u3 = 0,
/// Interrupt enable at trigger event overrun
OIE: u1 = 0x0,
reserved16: u7 = 0,
/// DMA request generator channel enable/disable
GE: u1 = 0x0,
/// DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input
GPOL: u2 = 0x0,
/// Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.
GNBREQ: u5 = 0x0,
padding: u8 = 0,
}),
/// DMAMux - DMA request generator channel x control register
/// offset: 0x104
RG1CR: mmio.Mmio(packed struct(u32) {
/// DMA request trigger input selected
SIG_ID: u5 = 0x0,
reserved8: u3 = 0,
/// Interrupt enable at trigger event overrun
OIE: u1 = 0x0,
reserved16: u7 = 0,
/// DMA request generator channel enable/disable
GE: u1 = 0x0,
/// DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input
GPOL: u2 = 0x0,
/// Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.
GNBREQ: u5 = 0x0,
padding: u8 = 0,
}),
/// DMAMux - DMA request generator channel x control register
/// offset: 0x108
RG2CR: mmio.Mmio(packed struct(u32) {
/// DMA request trigger input selected
SIG_ID: u5 = 0x0,
reserved8: u3 = 0,
/// Interrupt enable at trigger event overrun
OIE: u1 = 0x0,
reserved16: u7 = 0,
/// DMA request generator channel enable/disable
GE: u1 = 0x0,
/// DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input
GPOL: u2 = 0x0,
/// Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.
GNBREQ: u5 = 0x0,
padding: u8 = 0,
}),
/// DMAMux - DMA request generator channel x control register
/// offset: 0x10c
RG3CR: mmio.Mmio(packed struct(u32) {
/// DMA request trigger input selected
SIG_ID: u5 = 0x0,
reserved8: u3 = 0,
/// Interrupt enable at trigger event overrun
OIE: u1 = 0x0,
reserved16: u7 = 0,
/// DMA request generator channel enable/disable
GE: u1 = 0x0,
/// DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input
GPOL: u2 = 0x0,
/// Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset.
GNBREQ: u5 = 0x0,
padding: u8 = 0,
}),
/// offset: 0x110
reserved272: [48]u8,
/// DMAMux - DMA request generator status register
/// offset: 0x140
RGSR: mmio.Mmio(packed struct(u32) {
/// Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register.
OF: u4 = 0x0,
padding: u28 = 0,
}),
/// DMAMux - DMA request generator clear flag register
/// offset: 0x144
RGCFR: mmio.Mmio(packed struct(u32) {
/// Clear trigger event overrun flag Upon setting, this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register.
COF: u4 = 0x0,
padding: u28 = 0,
}),
};

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src/stm32g4/types/peripherals/EXTI.zig Normal file
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const microzig = @import("microzig");
const mmio = microzig.mmio;
const types = @import("../../types.zig");
/// External interrupt/event controller
pub const EXTI = extern struct {
/// Interrupt mask register
/// offset: 0x00
IMR1: mmio.Mmio(packed struct(u32) {
/// Interrupt Mask on line 0
IM0: u1 = 0x0,
/// Interrupt Mask on line 1
IM1: u1 = 0x0,
/// Interrupt Mask on line 2
IM2: u1 = 0x0,
/// Interrupt Mask on line 3
IM3: u1 = 0x0,
/// Interrupt Mask on line 4
IM4: u1 = 0x0,
/// Interrupt Mask on line 5
IM5: u1 = 0x0,
/// Interrupt Mask on line 6
IM6: u1 = 0x0,
/// Interrupt Mask on line 7
IM7: u1 = 0x0,
/// Interrupt Mask on line 8
IM8: u1 = 0x0,
/// Interrupt Mask on line 9
IM9: u1 = 0x0,
/// Interrupt Mask on line 10
IM10: u1 = 0x0,
/// Interrupt Mask on line 11
IM11: u1 = 0x0,
/// Interrupt Mask on line 12
IM12: u1 = 0x0,
/// Interrupt Mask on line 13
IM13: u1 = 0x0,
/// Interrupt Mask on line 14
IM14: u1 = 0x0,
/// Interrupt Mask on line 15
IM15: u1 = 0x0,
/// Interrupt Mask on line 16
IM16: u1 = 0x0,
/// Interrupt Mask on line 17
IM17: u1 = 0x1,
/// Interrupt Mask on line 18
IM18: u1 = 0x0,
/// Interrupt Mask on line 19
IM19: u1 = 0x0,
/// Interrupt Mask on line 20
IM20: u1 = 0x0,
/// Interrupt Mask on line 21
IM21: u1 = 0x0,
/// Interrupt Mask on line 22
IM22: u1 = 0x0,
/// Interrupt Mask on line 23
IM23: u1 = 0x1,
/// Interrupt Mask on line 24
IM24: u1 = 0x1,
/// Interrupt Mask on line 25
IM25: u1 = 0x1,
/// Interrupt Mask on line 26
IM26: u1 = 0x1,
/// Interrupt Mask on line 27
IM27: u1 = 0x1,
/// Interrupt Mask on line 28
IM28: u1 = 0x1,
/// Interrupt Mask on line 29
IM29: u1 = 0x1,
/// Interrupt Mask on line 30
IM30: u1 = 0x1,
/// Interrupt Mask on line 31
IM31: u1 = 0x1,
}),
/// Event mask register
/// offset: 0x04
EMR1: mmio.Mmio(packed struct(u32) {
/// Event Mask on line 0
EM0: u1 = 0x0,
/// Event Mask on line 1
EM1: u1 = 0x0,
/// Event Mask on line 2
EM2: u1 = 0x0,
/// Event Mask on line 3
EM3: u1 = 0x0,
/// Event Mask on line 4
EM4: u1 = 0x0,
/// Event Mask on line 5
EM5: u1 = 0x0,
/// Event Mask on line 6
EM6: u1 = 0x0,
/// Event Mask on line 7
EM7: u1 = 0x0,
/// Event Mask on line 8
EM8: u1 = 0x0,
/// Event Mask on line 9
EM9: u1 = 0x0,
/// Event Mask on line 10
EM10: u1 = 0x0,
/// Event Mask on line 11
EM11: u1 = 0x0,
/// Event Mask on line 12
EM12: u1 = 0x0,
/// Event Mask on line 13
EM13: u1 = 0x0,
/// Event Mask on line 14
EM14: u1 = 0x0,
/// Event Mask on line 15
EM15: u1 = 0x0,
/// Event Mask on line 16
EM16: u1 = 0x0,
/// Event Mask on line 17
EM17: u1 = 0x0,
/// Event Mask on line 18
EM18: u1 = 0x0,
/// Event Mask on line 19
EM19: u1 = 0x0,
/// Event Mask on line 20
EM20: u1 = 0x0,
/// Event Mask on line 21
EM21: u1 = 0x0,
/// Event Mask on line 22
EM22: u1 = 0x0,
/// Event Mask on line 23
EM23: u1 = 0x0,
/// Event Mask on line 24
EM24: u1 = 0x0,
/// Event Mask on line 25
EM25: u1 = 0x0,
/// Event Mask on line 26
EM26: u1 = 0x0,
/// Event Mask on line 27
EM27: u1 = 0x0,
/// Event Mask on line 28
EM28: u1 = 0x0,
/// Event Mask on line 29
EM29: u1 = 0x0,
/// Event Mask on line 30
EM30: u1 = 0x0,
/// Event Mask on line 31
EM31: u1 = 0x0,
}),
/// Rising Trigger selection register
/// offset: 0x08
RTSR1: mmio.Mmio(packed struct(u32) {
/// Rising trigger event configuration of line 0
RT0: u1 = 0x0,
/// Rising trigger event configuration of line 1
RT1: u1 = 0x0,
/// Rising trigger event configuration of line 2
RT2: u1 = 0x0,
/// Rising trigger event configuration of line 3
RT3: u1 = 0x0,
/// Rising trigger event configuration of line 4
RT4: u1 = 0x0,
/// Rising trigger event configuration of line 5
RT5: u1 = 0x0,
/// Rising trigger event configuration of line 6
RT6: u1 = 0x0,
/// Rising trigger event configuration of line 7
RT7: u1 = 0x0,
/// Rising trigger event configuration of line 8
RT8: u1 = 0x0,
/// Rising trigger event configuration of line 9
RT9: u1 = 0x0,
/// Rising trigger event configuration of line 10
RT10: u1 = 0x0,
/// Rising trigger event configuration of line 11
RT11: u1 = 0x0,
/// Rising trigger event configuration of line 12
RT12: u1 = 0x0,
/// Rising trigger event configuration of line 13
RT13: u1 = 0x0,
/// Rising trigger event configuration of line 14
RT14: u1 = 0x0,
/// Rising trigger event configuration of line 15
RT15: u1 = 0x0,
/// Rising trigger event configuration of line 16
RT16: u1 = 0x0,
reserved18: u1 = 0,
/// Rising trigger event configuration of line 18
RT18: u1 = 0x0,
/// Rising trigger event configuration of line 19
RT19: u1 = 0x0,
/// Rising trigger event configuration of line 20
RT20: u1 = 0x0,
/// Rising trigger event configuration of line 21
RT21: u1 = 0x0,
/// Rising trigger event configuration of line 22
RT22: u1 = 0x0,
reserved29: u6 = 0,
/// RT
RT: u3 = 0x0,
}),
/// Falling Trigger selection register
/// offset: 0x0c
FTSR1: mmio.Mmio(packed struct(u32) {
/// Falling trigger event configuration of line 0
FT0: u1 = 0x0,
/// Falling trigger event configuration of line 1
FT1: u1 = 0x0,
/// Falling trigger event configuration of line 2
FT2: u1 = 0x0,
/// Falling trigger event configuration of line 3
FT3: u1 = 0x0,
/// Falling trigger event configuration of line 4
FT4: u1 = 0x0,
/// Falling trigger event configuration of line 5
FT5: u1 = 0x0,
/// Falling trigger event configuration of line 6
FT6: u1 = 0x0,
/// Falling trigger event configuration of line 7
FT7: u1 = 0x0,
/// Falling trigger event configuration of line 8
FT8: u1 = 0x0,
/// Falling trigger event configuration of line 9
FT9: u1 = 0x0,
/// Falling trigger event configuration of line 10
FT10: u1 = 0x0,
/// Falling trigger event configuration of line 11
FT11: u1 = 0x0,
/// Falling trigger event configuration of line 12
FT12: u1 = 0x0,
/// Falling trigger event configuration of line 13
FT13: u1 = 0x0,
/// Falling trigger event configuration of line 14
FT14: u1 = 0x0,
/// Falling trigger event configuration of line 15
FT15: u1 = 0x0,
/// Falling trigger event configuration of line 16
FT16: u1 = 0x0,
reserved18: u1 = 0,
/// Falling trigger event configuration of line 18
FT18: u1 = 0x0,
/// Falling trigger event configuration of line 19
FT19: u1 = 0x0,
/// Falling trigger event configuration of line 20
FT20: u1 = 0x0,
/// Falling trigger event configuration of line 21
FT21: u1 = 0x0,
/// Falling trigger event configuration of line 22
FT22: u1 = 0x0,
padding: u9 = 0,
}),
/// Software interrupt event register
/// offset: 0x10
SWIER1: mmio.Mmio(packed struct(u32) {
/// Software Interrupt on line 0
SWI0: u1 = 0x0,
/// Software Interrupt on line 1
SWI1: u1 = 0x0,
/// Software Interrupt on line 2
SWI2: u1 = 0x0,
/// Software Interrupt on line 3
SWI3: u1 = 0x0,
/// Software Interrupt on line 4
SWI4: u1 = 0x0,
/// Software Interrupt on line 5
SWI5: u1 = 0x0,
/// Software Interrupt on line 6
SWI6: u1 = 0x0,
/// Software Interrupt on line 7
SWI7: u1 = 0x0,
/// Software Interrupt on line 8
SWI8: u1 = 0x0,
/// Software Interrupt on line 9
SWI9: u1 = 0x0,
/// Software Interrupt on line 10
SWI10: u1 = 0x0,
/// Software Interrupt on line 11
SWI11: u1 = 0x0,
/// Software Interrupt on line 12
SWI12: u1 = 0x0,
/// Software Interrupt on line 13
SWI13: u1 = 0x0,
/// Software Interrupt on line 14
SWI14: u1 = 0x0,
/// Software Interrupt on line 15
SWI15: u1 = 0x0,
/// Software Interrupt on line 16
SWI16: u1 = 0x0,
reserved18: u1 = 0,
/// Software Interrupt on line 18
SWI18: u1 = 0x0,
/// Software Interrupt on line 19
SWI19: u1 = 0x0,
/// Software Interrupt on line 20
SWI20: u1 = 0x0,
/// Software Interrupt on line 21
SWI21: u1 = 0x0,
/// Software Interrupt on line 22
SWI22: u1 = 0x0,
padding: u9 = 0,
}),
/// Pending register
/// offset: 0x14
PR1: mmio.Mmio(packed struct(u32) {
/// Pending bit 0
PIF0: u1 = 0x0,
/// Pending bit 1
PIF1: u1 = 0x0,
/// Pending bit 2
PIF2: u1 = 0x0,
/// Pending bit 3
PIF3: u1 = 0x0,
/// Pending bit 4
PIF4: u1 = 0x0,
/// Pending bit 5
PIF5: u1 = 0x0,
/// Pending bit 6
PIF6: u1 = 0x0,
/// Pending bit 7
PIF7: u1 = 0x0,
/// Pending bit 8
PIF8: u1 = 0x0,
/// Pending bit 9
PIF9: u1 = 0x0,
/// Pending bit 10
PIF10: u1 = 0x0,
/// Pending bit 11
PIF11: u1 = 0x0,
/// Pending bit 12
PIF12: u1 = 0x0,
/// Pending bit 13
PIF13: u1 = 0x0,
/// Pending bit 14
PIF14: u1 = 0x0,
/// Pending bit 15
PIF15: u1 = 0x0,
/// Pending bit 16
PIF16: u1 = 0x0,
/// Pending bit 17
PIF17: u1 = 0x0,
/// Pending bit 18
PIF18: u1 = 0x0,
/// Pending bit 19
PIF19: u1 = 0x0,
/// Pending bit 20
PIF20: u1 = 0x0,
/// Pending bit 21
PIF21: u1 = 0x0,
/// Pending bit 22
PIF22: u1 = 0x0,
reserved29: u6 = 0,
/// Pending bit 29
PIF29: u1 = 0x0,
/// Pending bit 30
PIF30: u1 = 0x0,
/// Pending bit 31
PIF31: u1 = 0x0,
}),
/// offset: 0x18
reserved24: [8]u8,
/// Interrupt mask register
/// offset: 0x20
IMR2: mmio.Mmio(packed struct(u32) {
/// Interrupt Mask on external/internal line 32
IM32: u1 = 0x1,
/// Interrupt Mask on external/internal line 33
IM33: u1 = 0x1,
/// Interrupt Mask on external/internal line 34
IM34: u1 = 0x1,
/// Interrupt Mask on external/internal line 35
IM35: u1 = 0x0,
/// Interrupt Mask on external/internal line 36
IM36: u1 = 0x0,
/// Interrupt Mask on external/internal line 37
IM37: u1 = 0x0,
/// Interrupt Mask on external/internal line 38
IM38: u1 = 0x0,
/// Interrupt Mask on external/internal line 39
IM39: u1 = 0x1,
/// Interrupt Mask on external/internal line 40
IM40: u1 = 0x1,
/// Interrupt Mask on external/internal line 41
IM41: u1 = 0x1,
/// Interrupt Mask on external/internal line 42
IM42: u1 = 0x1,
/// Interrupt Mask on external/internal line 43
IM43: u1 = 0x1,
padding: u20 = 0,
}),
/// Event mask register
/// offset: 0x24
EMR2: mmio.Mmio(packed struct(u32) {
/// Event mask on external/internal line 32
EM32: u1 = 0x0,
/// Event mask on external/internal line 33
EM33: u1 = 0x0,
/// Event mask on external/internal line 34
EM34: u1 = 0x0,
/// Event mask on external/internal line 35
EM35: u1 = 0x0,
/// Event mask on external/internal line 36
EM36: u1 = 0x0,
/// Event mask on external/internal line 37
EM37: u1 = 0x0,
/// Event mask on external/internal line 38
EM38: u1 = 0x0,
/// Event mask on external/internal line 39
EM39: u1 = 0x0,
/// Event mask on external/internal line 40
EM40: u1 = 0x0,
padding: u23 = 0,
}),
/// Rising Trigger selection register
/// offset: 0x28
RTSR2: mmio.Mmio(packed struct(u32) {
/// Rising trigger event configuration bit of line 32
RT32: u1 = 0x0,
/// Rising trigger event configuration bit of line 32
RT33: u1 = 0x0,
reserved6: u4 = 0,
/// Rising trigger event configuration bit of line 38
RT38: u1 = 0x0,
/// Rising trigger event configuration bit of line 39
RT39: u1 = 0x0,
/// Rising trigger event configuration bit of line 40
RT40: u1 = 0x0,
/// Rising trigger event configuration bit of line 41
RT41: u1 = 0x0,
padding: u22 = 0,
}),
/// Falling Trigger selection register
/// offset: 0x2c
FTSR2: mmio.Mmio(packed struct(u32) {
reserved3: u3 = 0,
/// Falling trigger event configuration bit of line 35
FT35: u1 = 0x0,
/// Falling trigger event configuration bit of line 36
FT36: u1 = 0x0,
/// Falling trigger event configuration bit of line 37
FT37: u1 = 0x0,
/// Falling trigger event configuration bit of line 38
FT38: u1 = 0x0,
padding: u25 = 0,
}),
/// Software interrupt event register
/// offset: 0x30
SWIER2: mmio.Mmio(packed struct(u32) {
reserved3: u3 = 0,
/// Software interrupt on line 35
SWI35: u1 = 0x0,
/// Software interrupt on line 36
SWI36: u1 = 0x0,
/// Software interrupt on line 37
SWI37: u1 = 0x0,
/// Software interrupt on line 38
SWI38: u1 = 0x0,
padding: u25 = 0,
}),
/// Pending register
/// offset: 0x34
PR2: mmio.Mmio(packed struct(u32) {
reserved3: u3 = 0,
/// Pending interrupt flag on line 35
PIF35: u1 = 0x0,
/// Pending interrupt flag on line 36
PIF36: u1 = 0x0,
/// Pending interrupt flag on line 37
PIF37: u1 = 0x0,
/// Pending interrupt flag on line 38
PIF38: u1 = 0x0,
padding: u25 = 0,
}),
};

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src/stm32g4/types/peripherals/FDCAN.zig Normal file
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src/stm32g4/types/peripherals/FLASH.zig Normal file
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const microzig = @import("microzig");
const mmio = microzig.mmio;
const types = @import("../../types.zig");
/// Flash
pub const FLASH = extern struct {
/// Flash access control register
/// offset: 0x00
FLASH_ACR: mmio.Mmio(packed struct(u32) {
/// Latency
LATENCY: enum(u4) {
/// Zero wait state
B_0x0 = 0x0,
/// One wait state
B_0x1 = 0x1,
/// Two wait states
B_0x2 = 0x2,
/// Three wait states
B_0x3 = 0x3,
/// Four wait states
B_0x4 = 0x4,
_,
} = .B_0x1,
reserved8: u4 = 0,
/// Prefetch enable
PRFTEN: enum(u1) {
/// Prefetch disabled
B_0x0 = 0x0,
/// Prefetch enabled
B_0x1 = 0x1,
} = .B_0x0,
/// Instruction cache enable
ICEN: enum(u1) {
/// Instruction cache is disabled
B_0x0 = 0x0,
/// Instruction cache is enabled
B_0x1 = 0x1,
} = .B_0x1,
/// Data cache enable
DCEN: enum(u1) {
/// Data cache is disabled
B_0x0 = 0x0,
/// Data cache is enabled
B_0x1 = 0x1,
} = .B_0x1,
/// Instruction cache reset
ICRST: enum(u1) {
/// Instruction cache is not reset
B_0x0 = 0x0,
/// Instruction cache is reset
B_0x1 = 0x1,
} = .B_0x0,
/// Data cache reset
DCRST: enum(u1) {
/// Data cache is not reset
B_0x0 = 0x0,
/// Data cache is reset
B_0x1 = 0x1,
} = .B_0x0,
/// Flash Power-down mode during Run or Low-power run mode
RUN_PD: enum(u1) {
/// Flash in Idle mode
B_0x0 = 0x0,
/// Flash in Power-down mode
B_0x1 = 0x1,
} = .B_0x0,
/// Flash Power-down mode during Sleep or Low-power sleep mode
SLEEP_PD: enum(u1) {
/// Flash in Idle mode during Sleep and Low-power sleep modes
B_0x0 = 0x0,
/// Flash in Power-down mode during Sleep and Low-power sleep modes
B_0x1 = 0x1,
} = .B_0x0,
reserved18: u3 = 0,
/// Debug software enable
DBG_SWEN: enum(u1) {
/// Debugger disabled
B_0x0 = 0x0,
/// Debugger enabled
B_0x1 = 0x1,
} = .B_0x1,
padding: u13 = 0,
}),
/// Flash Power-down key register
/// offset: 0x04
FLASH_PDKEYR: mmio.Mmio(packed struct(u32) {
/// Power-down in Run mode Flash key
PDKEYR: u32 = 0x0,
}),
/// Flash key register
/// offset: 0x08
FLASH_KEYR: mmio.Mmio(packed struct(u32) {
/// Flash key
KEYR: u32 = 0x0,
}),
/// Flash option key register
/// offset: 0x0c
FLASH_OPTKEYR: mmio.Mmio(packed struct(u32) {
/// Option byte key
OPTKEYR: u32 = 0x0,
}),
/// Flash status register
/// offset: 0x10
FLASH_SR: mmio.Mmio(packed struct(u32) {
/// End of operation
EOP: u1 = 0x0,
/// Operation error
OPERR: u1 = 0x0,
reserved3: u1 = 0,
/// Programming error
PROGERR: u1 = 0x0,
/// Write protection error
WRPERR: u1 = 0x0,
/// Programming alignment error
PGAERR: u1 = 0x0,
/// Size error
SIZERR: u1 = 0x0,
/// Programming sequence error
PGSERR: u1 = 0x0,
/// Fast programming data miss error
MISSERR: u1 = 0x0,
/// Fast programming error
FASTERR: u1 = 0x0,
reserved14: u4 = 0,
/// PCROP read error
RDERR: u1 = 0x0,
/// Option validity error
OPTVERR: u1 = 0x0,
/// Busy
BSY: u1 = 0x0,
padding: u15 = 0,
}),
/// Flash control register
/// offset: 0x14
FLASH_CR: mmio.Mmio(packed struct(u32) {
/// Programming
PG: enum(u1) {
/// Flash programming disabled
B_0x0 = 0x0,
/// Flash programming enabled
B_0x1 = 0x1,
} = .B_0x0,
/// Page erase
PER: enum(u1) {
/// page erase disabled
B_0x0 = 0x0,
/// page erase enabled
B_0x1 = 0x1,
} = .B_0x0,
/// Mass erase
MER1: u1 = 0x0,
/// Page number selection
PNB: enum(u6) {
/// page 0
B_0x0 = 0x0,
/// page 1
B_0x1 = 0x1,
_,
} = .B_0x0,
reserved16: u7 = 0,
/// None
STRT: u1 = 0x0,
/// Options modification start
OPTSTRT: u1 = 0x0,
/// Fast programming
FSTPG: enum(u1) {
/// Fast programming disabled
B_0x0 = 0x0,
/// Fast programming enabled
B_0x1 = 0x1,
} = .B_0x0,
reserved24: u5 = 0,
/// End of operation interrupt enable
EOPIE: enum(u1) {
/// EOP Interrupt disabled
B_0x0 = 0x0,
/// EOP Interrupt enabled
B_0x1 = 0x1,
} = .B_0x0,
/// Error interrupt enable
ERRIE: enum(u1) {
/// OPERR error interrupt disabled
B_0x0 = 0x0,
/// OPERR error interrupt enabled
B_0x1 = 0x1,
} = .B_0x0,
/// PCROP read error interrupt enable
RDERRIE: enum(u1) {
/// PCROP read error interrupt disabled
B_0x0 = 0x0,
/// PCROP read error interrupt enabled
B_0x1 = 0x1,
} = .B_0x0,
/// Force the option byte loading
OBL_LAUNCH: enum(u1) {
/// Option byte loading complete
B_0x0 = 0x0,
/// Option byte loading requested
B_0x1 = 0x1,
} = .B_0x0,
/// Securable memory area protection bit.
SEC_PROT1: u1 = 0x0,
reserved30: u1 = 0,
/// Options Lock
OPTLOCK: u1 = 0x1,
/// FLASH_CR Lock
LOCK: u1 = 0x1,
}),
/// Flash ECC register
/// offset: 0x18
FLASH_ECCR: mmio.Mmio(packed struct(u32) {
/// ECC fail address
ADDR_ECC: u19 = 0x0,
reserved22: u3 = 0,
/// System Flash ECC fail
SYSF_ECC: u1 = 0x0,
reserved24: u1 = 0,
/// None
ECCCIE: u1 = 0x0,
reserved30: u5 = 0,
/// ECC correction
ECCC: u1 = 0x0,
/// ECC detection
ECCD: u1 = 0x0,
}),
/// offset: 0x1c
reserved28: [4]u8,
/// offset: 0x20
FLASH_OPTR: mmio.Mmio(packed struct(u32) {
/// Read protection level
RDP: enum(u8) {
/// Level 0, read protection not active
B_0xAA = 0xaa,
/// Level 2, chip read protection active
B_0xCC = 0xcc,
_,
} = @enumFromInt(0x0),
/// BOR reset Level
BOR_LEV: enum(u3) {
/// BOR Level 0. Reset level threshold is around 1.7 V
B_0x0 = 0x0,
/// BOR Level 1. Reset level threshold is around 2.0 V
B_0x1 = 0x1,
/// BOR Level 2. Reset level threshold is around 2.2 V
B_0x2 = 0x2,
/// BOR Level 3. Reset level threshold is around 2.5 V
B_0x3 = 0x3,
/// BOR Level 4. Reset level threshold is around 2.8 V
B_0x4 = 0x4,
_,
} = .B_0x0,
reserved12: u1 = 0,
/// None
nRST_STOP: u1 = 0x0,
/// None
nRST_STDBY: u1 = 0x0,
/// None
nRST_SHDW: u1 = 0x0,
reserved16: u1 = 0,
/// Independent watchdog selection
IWDG_SW: enum(u1) {
/// Hardware independent watchdog
B_0x0 = 0x0,
/// Software independent watchdog
B_0x1 = 0x1,
} = .B_0x0,
/// Independent watchdog counter freeze in Stop mode
IWDG_STOP: enum(u1) {
/// Independent watchdog counter is frozen in Stop mode
B_0x0 = 0x0,
/// Independent watchdog counter is running in Stop mode
B_0x1 = 0x1,
} = .B_0x0,
/// None
IWGD_STDBY: u1 = 0x0,
/// Window watchdog selection
WWDG_SW: enum(u1) {
/// Hardware window watchdog
B_0x0 = 0x0,
/// Software window watchdog
B_0x1 = 0x1,
} = .B_0x0,
reserved23: u3 = 0,
/// Boot configuration
nBOOT1: u1 = 0x0,
/// SRAM1 and CCM SRAM parity check enable
SRAM_PE: enum(u1) {
/// SRAM1 and CCM SRAM parity check enable
B_0x0 = 0x0,
/// SRAM1 and CCM SRAM parity check disable
B_0x1 = 0x1,
} = .B_0x0,
/// None
CCMSRAM_RST: u1 = 0x0,
/// Software BOOT0
nSWBOOT0: enum(u1) {
/// BOOT0 taken from the option bit nBOOT0
B_0x0 = 0x0,
/// BOOT0 taken from PB8/BOOT0 pin
B_0x1 = 0x1,
} = .B_0x0,
/// nBOOT0 option bit
nBOOT0: enum(u1) {
/// nBOOT0 = 0
B_0x0 = 0x0,
/// nBOOT0 = 1
B_0x1 = 0x1,
} = .B_0x0,
/// None
NRST_MODE: enum(u2) {
/// Reset Input only: a low level on the NRST pin generates system reset, internal RESET not propagated to the NSRT pin
B_0x1 = 0x1,
/// GPIO: standard GPIO pad functionality, only internal RESET possible
B_0x2 = 0x2,
/// Bidirectional reset: NRST pin configured in reset input/output mode (legacy mode)
B_0x3 = 0x3,
_,
} = @enumFromInt(0x0),
/// Internal reset holder enable bit
IRHEN: enum(u1) {
/// Internal resets are propagated as simple pulse on NRST pin
B_0x0 = 0x0,
/// Internal resets drives NRST pin low until it is seen as low level
B_0x1 = 0x1,
} = .B_0x0,
padding: u1 = 0,
}),
/// Flash PCROP1 Start address register
/// offset: 0x24
FLASH_PCROP1SR: mmio.Mmio(packed struct(u32) {
/// PCROP area start offset
PCROP1_STRT: u15,
padding: u17 = 0,
}),
/// Flash PCROP1 End address register
/// offset: 0x28
FLASH_PCROP1ER: mmio.Mmio(packed struct(u32) {
/// PCROP area end offset
PCROP1_END: u15,
reserved31: u16 = 0,
/// PCROP area preserved when RDP level decreased
PCROP_RDP: enum(u1) {
/// PCROP area is not erased when the RDP level is decreased from Level 1 to Level 0.
B_0x0 = 0x0,
/// PCROP area is erased when the RDP level is decreased from Level 1 to Level 0 (full mass erase).
B_0x1 = 0x1,
},
}),
/// Flash WRP area A address register
/// offset: 0x2c
FLASH_WRP1AR: mmio.Mmio(packed struct(u32) {
/// WRP first area A start offset
WRP1A_STRT: u6,
reserved16: u10 = 0,
/// WRP first area A end offset
WRP1A_END: u6,
padding: u10 = 0,
}),
/// Flash WRP area B address register
/// offset: 0x30
FLASH_WRP1BR: mmio.Mmio(packed struct(u32) {
/// WRP second area B start offset
WRP1B_STRT: u6,
reserved16: u10 = 0,
/// WRP second area B end offset
WRP1B_END: u6,
padding: u10 = 0,
}),
/// offset: 0x34
reserved52: [60]u8,
/// Flash Securable area register
/// offset: 0x70
FLASH_SEC1R: mmio.Mmio(packed struct(u32) {
/// sets the number of pages used in the Securable area.
SEC_SIZE1: u7,
reserved16: u9 = 0,
/// used to force boot from user Flash area
BOOT_LOCK: enum(u1) {
/// Boot based on the pad/option bit configuration
B_0x0 = 0x0,
/// Boot forced from Main Flash memory
B_0x1 = 0x1,
},
padding: u15 = 0,
}),
};

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src/stm32g4/types/peripherals/FMAC.zig Normal file
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const microzig = @import("microzig");
const mmio = microzig.mmio;
const types = @import("../../types.zig");
/// Filter Math Accelerator
pub const FMAC = extern struct {
/// FMAC X1 Buffer Configuration register
/// offset: 0x00
X1BUFCFG: mmio.Mmio(packed struct(u32) {
/// X1_BASE
X1_BASE: u8 = 0x0,
/// X1_BUF_SIZE
X1_BUF_SIZE: u8 = 0x0,
reserved24: u8 = 0,
/// FULL_WM
FULL_WM: u2 = 0x0,
padding: u6 = 0,
}),
/// FMAC X2 Buffer Configuration register
/// offset: 0x04
X2BUFCFG: mmio.Mmio(packed struct(u32) {
/// X1_BASE
X2_BASE: u8 = 0x0,
/// X1_BUF_SIZE
X2_BUF_SIZE: u8 = 0x0,
padding: u16 = 0,
}),
/// FMAC Y Buffer Configuration register
/// offset: 0x08
YBUFCFG: mmio.Mmio(packed struct(u32) {
/// X1_BASE
Y_BASE: u8 = 0x0,
/// X1_BUF_SIZE
Y_BUF_SIZE: u8 = 0x0,
reserved24: u8 = 0,
/// EMPTY_WM
EMPTY_WM: u2 = 0x0,
padding: u6 = 0,
}),
/// FMAC Parameter register
/// offset: 0x0c
PARAM: mmio.Mmio(packed struct(u32) {
/// P
P: u8 = 0x0,
/// Q
Q: u8 = 0x0,
/// R
R: u8 = 0x0,
/// FUNC
FUNC: u7 = 0x0,
/// START
START: u1 = 0x0,
}),
/// FMAC Control register
/// offset: 0x10
CR: mmio.Mmio(packed struct(u32) {
/// RIEN
RIEN: u1 = 0x0,
/// WIEN
WIEN: u1 = 0x0,
/// OVFLIEN
OVFLIEN: u1 = 0x0,
/// UNFLIEN
UNFLIEN: u1 = 0x0,
/// SATIEN
SATIEN: u1 = 0x0,
reserved8: u3 = 0,
/// DMAREN
DMAREN: u1 = 0x0,
/// DMAWEN
DMAWEN: u1 = 0x0,
reserved15: u5 = 0,
/// CLIPEN
CLIPEN: u1 = 0x0,
/// RESET
RESET: u1 = 0x0,
padding: u15 = 0,
}),
/// FMAC Status register
/// offset: 0x14
SR: mmio.Mmio(packed struct(u32) {
/// YEMPTY
YEMPTY: u1 = 0x0,
/// X1FULL
X1FULL: u1 = 0x0,
reserved8: u6 = 0,
/// OVFL
OVFL: u1 = 0x0,
/// UNFL
UNFL: u1 = 0x0,
/// SAT
SAT: u1 = 0x0,
padding: u21 = 0,
}),
/// FMAC Write Data register
/// offset: 0x18
WDATA: mmio.Mmio(packed struct(u32) {
/// WDATA
WDATA: u16 = 0x0,
padding: u16 = 0,
}),
/// FMAC Read Data register
/// offset: 0x1c
RDATA: mmio.Mmio(packed struct(u32) {
/// RDATA
RDATA: u16 = 0x0,
padding: u16 = 0,
}),
};

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src/stm32g4/types/peripherals/GPIOA.zig Normal file
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const microzig = @import("microzig");
const mmio = microzig.mmio;
const types = @import("../../types.zig");
/// General-purpose I/Os
pub const GPIOA = extern struct {
/// GPIO port mode register
/// offset: 0x00
MODER: mmio.Mmio(packed struct(u32) {
/// Port x configuration bits (y = 0..15)
MODER0: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
MODER1: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
MODER2: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
MODER3: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
MODER4: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
MODER5: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
MODER6: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
MODER7: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
MODER8: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
MODER9: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
MODER10: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
MODER11: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
MODER12: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
MODER13: u2 = 0x2,
/// Port x configuration bits (y = 0..15)
MODER14: u2 = 0x2,
/// Port x configuration bits (y = 0..15)
MODER15: u2 = 0x2,
}),
/// GPIO port output type register
/// offset: 0x04
OTYPER: mmio.Mmio(packed struct(u32) {
/// Port x configuration bits (y = 0..15)
OT0: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT1: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT2: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT3: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT4: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT5: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT6: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT7: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT8: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT9: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT10: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT11: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT12: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT13: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT14: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT15: u1 = 0x0,
padding: u16 = 0,
}),
/// GPIO port output speed register
/// offset: 0x08
OSPEEDR: mmio.Mmio(packed struct(u32) {
/// Port x configuration bits (y = 0..15)
OSPEEDR0: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR1: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR2: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR3: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR4: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR5: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR6: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR7: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR8: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR9: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR10: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR11: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR12: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR13: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
OSPEEDR14: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR15: u2 = 0x0,
}),
/// GPIO port pull-up/pull-down register
/// offset: 0x0c
PUPDR: mmio.Mmio(packed struct(u32) {
/// Port x configuration bits (y = 0..15)
PUPDR0: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR1: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR2: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR3: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR4: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR5: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR6: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR7: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR8: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR9: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR10: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR11: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR12: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR13: u2 = 0x1,
/// Port x configuration bits (y = 0..15)
PUPDR14: u2 = 0x2,
/// Port x configuration bits (y = 0..15)
PUPDR15: u2 = 0x1,
}),
/// GPIO port input data register
/// offset: 0x10
IDR: mmio.Mmio(packed struct(u32) {
/// Port input data (y = 0..15)
IDR0: u1 = 0x0,
/// Port input data (y = 0..15)
IDR1: u1 = 0x0,
/// Port input data (y = 0..15)
IDR2: u1 = 0x0,
/// Port input data (y = 0..15)
IDR3: u1 = 0x0,
/// Port input data (y = 0..15)
IDR4: u1 = 0x0,
/// Port input data (y = 0..15)
IDR5: u1 = 0x0,
/// Port input data (y = 0..15)
IDR6: u1 = 0x0,
/// Port input data (y = 0..15)
IDR7: u1 = 0x0,
/// Port input data (y = 0..15)
IDR8: u1 = 0x0,
/// Port input data (y = 0..15)
IDR9: u1 = 0x0,
/// Port input data (y = 0..15)
IDR10: u1 = 0x0,
/// Port input data (y = 0..15)
IDR11: u1 = 0x0,
/// Port input data (y = 0..15)
IDR12: u1 = 0x0,
/// Port input data (y = 0..15)
IDR13: u1 = 0x0,
/// Port input data (y = 0..15)
IDR14: u1 = 0x0,
/// Port input data (y = 0..15)
IDR15: u1 = 0x0,
padding: u16 = 0,
}),
/// GPIO port output data register
/// offset: 0x14
ODR: mmio.Mmio(packed struct(u32) {
/// Port output data (y = 0..15)
ODR0: u1 = 0x0,
/// Port output data (y = 0..15)
ODR1: u1 = 0x0,
/// Port output data (y = 0..15)
ODR2: u1 = 0x0,
/// Port output data (y = 0..15)
ODR3: u1 = 0x0,
/// Port output data (y = 0..15)
ODR4: u1 = 0x0,
/// Port output data (y = 0..15)
ODR5: u1 = 0x0,
/// Port output data (y = 0..15)
ODR6: u1 = 0x0,
/// Port output data (y = 0..15)
ODR7: u1 = 0x0,
/// Port output data (y = 0..15)
ODR8: u1 = 0x0,
/// Port output data (y = 0..15)
ODR9: u1 = 0x0,
/// Port output data (y = 0..15)
ODR10: u1 = 0x0,
/// Port output data (y = 0..15)
ODR11: u1 = 0x0,
/// Port output data (y = 0..15)
ODR12: u1 = 0x0,
/// Port output data (y = 0..15)
ODR13: u1 = 0x0,
/// Port output data (y = 0..15)
ODR14: u1 = 0x0,
/// Port output data (y = 0..15)
ODR15: u1 = 0x0,
padding: u16 = 0,
}),
/// GPIO port bit set/reset register
/// offset: 0x18
BSRR: mmio.Mmio(packed struct(u32) {
/// Port x set bit y (y= 0..15)
BS0: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS1: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS2: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS3: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS4: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS5: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS6: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS7: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS8: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS9: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS10: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS11: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS12: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS13: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS14: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS15: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BR0: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR1: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR2: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR3: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR4: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR5: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR6: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR7: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR8: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR9: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR10: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR11: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR12: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR13: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR14: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR15: u1 = 0x0,
}),
/// GPIO port configuration lock register
/// offset: 0x1c
LCKR: mmio.Mmio(packed struct(u32) {
/// Port x lock bit y (y= 0..15)
LCK0: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK1: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK2: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK3: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK4: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK5: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK6: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK7: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK8: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK9: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK10: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK11: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK12: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK13: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK14: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK15: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCKK: u1 = 0x0,
padding: u15 = 0,
}),
/// GPIO alternate function low register
/// offset: 0x20
AFRL: mmio.Mmio(packed struct(u32) {
/// Alternate function selection for port x bit y (y = 0..7)
AFRL0: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 0..7)
AFRL1: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 0..7)
AFRL2: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 0..7)
AFRL3: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 0..7)
AFRL4: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 0..7)
AFRL5: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 0..7)
AFRL6: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 0..7)
AFRL7: u4 = 0x0,
}),
/// GPIO alternate function high register
/// offset: 0x24
AFRH: mmio.Mmio(packed struct(u32) {
/// Alternate function selection for port x bit y (y = 8..15)
AFRH8: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 8..15)
AFRH9: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 8..15)
AFRH10: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 8..15)
AFRH11: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 8..15)
AFRH12: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 8..15)
AFRH13: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 8..15)
AFRH14: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 8..15)
AFRH15: u4 = 0x0,
}),
/// GPIO port bit reset register
/// offset: 0x28
BRR: mmio.Mmio(packed struct(u32) {
/// Port Reset bit
BR0: u1 = 0x0,
/// Port Reset bit
BR1: u1 = 0x0,
/// Port Reset bit
BR2: u1 = 0x0,
/// Port Reset bit
BR3: u1 = 0x0,
/// Port Reset bit
BR4: u1 = 0x0,
/// Port Reset bit
BR5: u1 = 0x0,
/// Port Reset bit
BR6: u1 = 0x0,
/// Port Reset bit
BR7: u1 = 0x0,
/// Port Reset bit
BR8: u1 = 0x0,
/// Port Reset bit
BR9: u1 = 0x0,
/// Port Reset bit
BR10: u1 = 0x0,
/// Port Reset bit
BR11: u1 = 0x0,
/// Port Reset bit
BR12: u1 = 0x0,
/// Port Reset bit
BR13: u1 = 0x0,
/// Port Reset bit
BR14: u1 = 0x0,
/// Port Reset bit
BR15: u1 = 0x0,
padding: u16 = 0,
}),
};

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src/stm32g4/types/peripherals/GPIOB.zig Normal file
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const microzig = @import("microzig");
const mmio = microzig.mmio;
const types = @import("../../types.zig");
/// General-purpose I/Os
pub const GPIOB = extern struct {
/// GPIO port mode register
/// offset: 0x00
MODER: mmio.Mmio(packed struct(u32) {
/// Port x configuration bits (y = 0..15)
MODER0: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
MODER1: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
MODER2: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
MODER3: u2 = 0x2,
/// Port x configuration bits (y = 0..15)
MODER4: u2 = 0x2,
/// Port x configuration bits (y = 0..15)
MODER5: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
MODER6: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
MODER7: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
MODER8: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
MODER9: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
MODER10: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
MODER11: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
MODER12: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
MODER13: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
MODER14: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
MODER15: u2 = 0x3,
}),
/// GPIO port output type register
/// offset: 0x04
OTYPER: mmio.Mmio(packed struct(u32) {
/// Port x configuration bits (y = 0..15)
OT0: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT1: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT2: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT3: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT4: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT5: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT6: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT7: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT8: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT9: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT10: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT11: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT12: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT13: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT14: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT15: u1 = 0x0,
padding: u16 = 0,
}),
/// GPIO port output speed register
/// offset: 0x08
OSPEEDR: mmio.Mmio(packed struct(u32) {
/// Port x configuration bits (y = 0..15)
OSPEEDR0: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR1: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR2: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR3: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
OSPEEDR4: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR5: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR6: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR7: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR8: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR9: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR10: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR11: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR12: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR13: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR14: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR15: u2 = 0x0,
}),
/// GPIO port pull-up/pull-down register
/// offset: 0x0c
PUPDR: mmio.Mmio(packed struct(u32) {
/// Port x configuration bits (y = 0..15)
PUPDR0: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR1: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR2: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR3: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR4: u2 = 0x1,
/// Port x configuration bits (y = 0..15)
PUPDR5: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR6: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR7: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR8: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR9: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR10: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR11: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR12: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR13: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR14: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR15: u2 = 0x0,
}),
/// GPIO port input data register
/// offset: 0x10
IDR: mmio.Mmio(packed struct(u32) {
/// Port input data (y = 0..15)
IDR0: u1 = 0x0,
/// Port input data (y = 0..15)
IDR1: u1 = 0x0,
/// Port input data (y = 0..15)
IDR2: u1 = 0x0,
/// Port input data (y = 0..15)
IDR3: u1 = 0x0,
/// Port input data (y = 0..15)
IDR4: u1 = 0x0,
/// Port input data (y = 0..15)
IDR5: u1 = 0x0,
/// Port input data (y = 0..15)
IDR6: u1 = 0x0,
/// Port input data (y = 0..15)
IDR7: u1 = 0x0,
/// Port input data (y = 0..15)
IDR8: u1 = 0x0,
/// Port input data (y = 0..15)
IDR9: u1 = 0x0,
/// Port input data (y = 0..15)
IDR10: u1 = 0x0,
/// Port input data (y = 0..15)
IDR11: u1 = 0x0,
/// Port input data (y = 0..15)
IDR12: u1 = 0x0,
/// Port input data (y = 0..15)
IDR13: u1 = 0x0,
/// Port input data (y = 0..15)
IDR14: u1 = 0x0,
/// Port input data (y = 0..15)
IDR15: u1 = 0x0,
padding: u16 = 0,
}),
/// GPIO port output data register
/// offset: 0x14
ODR: mmio.Mmio(packed struct(u32) {
/// Port output data (y = 0..15)
ODR0: u1 = 0x0,
/// Port output data (y = 0..15)
ODR1: u1 = 0x0,
/// Port output data (y = 0..15)
ODR2: u1 = 0x0,
/// Port output data (y = 0..15)
ODR3: u1 = 0x0,
/// Port output data (y = 0..15)
ODR4: u1 = 0x0,
/// Port output data (y = 0..15)
ODR5: u1 = 0x0,
/// Port output data (y = 0..15)
ODR6: u1 = 0x0,
/// Port output data (y = 0..15)
ODR7: u1 = 0x0,
/// Port output data (y = 0..15)
ODR8: u1 = 0x0,
/// Port output data (y = 0..15)
ODR9: u1 = 0x0,
/// Port output data (y = 0..15)
ODR10: u1 = 0x0,
/// Port output data (y = 0..15)
ODR11: u1 = 0x0,
/// Port output data (y = 0..15)
ODR12: u1 = 0x0,
/// Port output data (y = 0..15)
ODR13: u1 = 0x0,
/// Port output data (y = 0..15)
ODR14: u1 = 0x0,
/// Port output data (y = 0..15)
ODR15: u1 = 0x0,
padding: u16 = 0,
}),
/// GPIO port bit set/reset register
/// offset: 0x18
BSRR: mmio.Mmio(packed struct(u32) {
/// Port x set bit y (y= 0..15)
BS0: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS1: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS2: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS3: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS4: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS5: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS6: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS7: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS8: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS9: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS10: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS11: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS12: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS13: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS14: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS15: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BR0: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR1: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR2: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR3: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR4: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR5: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR6: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR7: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR8: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR9: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR10: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR11: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR12: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR13: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR14: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR15: u1 = 0x0,
}),
/// GPIO port configuration lock register
/// offset: 0x1c
LCKR: mmio.Mmio(packed struct(u32) {
/// Port x lock bit y (y= 0..15)
LCK0: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK1: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK2: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK3: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK4: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK5: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK6: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK7: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK8: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK9: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK10: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK11: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK12: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK13: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK14: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK15: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCKK: u1 = 0x0,
padding: u15 = 0,
}),
/// GPIO alternate function low register
/// offset: 0x20
AFRL: mmio.Mmio(packed struct(u32) {
/// Alternate function selection for port x bit y (y = 0..7)
AFRL0: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 0..7)
AFRL1: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 0..7)
AFRL2: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 0..7)
AFRL3: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 0..7)
AFRL4: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 0..7)
AFRL5: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 0..7)
AFRL6: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 0..7)
AFRL7: u4 = 0x0,
}),
/// GPIO alternate function high register
/// offset: 0x24
AFRH: mmio.Mmio(packed struct(u32) {
/// Alternate function selection for port x bit y (y = 8..15)
AFRH8: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 8..15)
AFRH9: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 8..15)
AFRH10: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 8..15)
AFRH11: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 8..15)
AFRH12: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 8..15)
AFRH13: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 8..15)
AFRH14: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 8..15)
AFRH15: u4 = 0x0,
}),
/// GPIO port bit reset register
/// offset: 0x28
BRR: mmio.Mmio(packed struct(u32) {
/// Port Reset bit
BR0: u1 = 0x0,
/// Port Reset bit
BR1: u1 = 0x0,
/// Port Reset bit
BR2: u1 = 0x0,
/// Port Reset bit
BR3: u1 = 0x0,
/// Port Reset bit
BR4: u1 = 0x0,
/// Port Reset bit
BR5: u1 = 0x0,
/// Port Reset bit
BR6: u1 = 0x0,
/// Port Reset bit
BR7: u1 = 0x0,
/// Port Reset bit
BR8: u1 = 0x0,
/// Port Reset bit
BR9: u1 = 0x0,
/// Port Reset bit
BR10: u1 = 0x0,
/// Port Reset bit
BR11: u1 = 0x0,
/// Port Reset bit
BR12: u1 = 0x0,
/// Port Reset bit
BR13: u1 = 0x0,
/// Port Reset bit
BR14: u1 = 0x0,
/// Port Reset bit
BR15: u1 = 0x0,
padding: u16 = 0,
}),
};

411
src/stm32g4/types/peripherals/GPIOC.zig Normal file
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const microzig = @import("microzig");
const mmio = microzig.mmio;
const types = @import("../../types.zig");
/// General-purpose I/Os
pub const GPIOC = extern struct {
/// GPIO port mode register
/// offset: 0x00
MODER: mmio.Mmio(packed struct(u32) {
/// Port x configuration bits (y = 0..15)
MODER0: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
MODER1: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
MODER2: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
MODER3: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
MODER4: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
MODER5: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
MODER6: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
MODER7: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
MODER8: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
MODER9: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
MODER10: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
MODER11: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
MODER12: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
MODER13: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
MODER14: u2 = 0x3,
/// Port x configuration bits (y = 0..15)
MODER15: u2 = 0x3,
}),
/// GPIO port output type register
/// offset: 0x04
OTYPER: mmio.Mmio(packed struct(u32) {
/// Port x configuration bits (y = 0..15)
OT0: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT1: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT2: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT3: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT4: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT5: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT6: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT7: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT8: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT9: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT10: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT11: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT12: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT13: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT14: u1 = 0x0,
/// Port x configuration bits (y = 0..15)
OT15: u1 = 0x0,
padding: u16 = 0,
}),
/// GPIO port output speed register
/// offset: 0x08
OSPEEDR: mmio.Mmio(packed struct(u32) {
/// Port x configuration bits (y = 0..15)
OSPEEDR0: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR1: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR2: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR3: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR4: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR5: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR6: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR7: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR8: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR9: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR10: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR11: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR12: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR13: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR14: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
OSPEEDR15: u2 = 0x0,
}),
/// GPIO port pull-up/pull-down register
/// offset: 0x0c
PUPDR: mmio.Mmio(packed struct(u32) {
/// Port x configuration bits (y = 0..15)
PUPDR0: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR1: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR2: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR3: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR4: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR5: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR6: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR7: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR8: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR9: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR10: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR11: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR12: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR13: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR14: u2 = 0x0,
/// Port x configuration bits (y = 0..15)
PUPDR15: u2 = 0x0,
}),
/// GPIO port input data register
/// offset: 0x10
IDR: mmio.Mmio(packed struct(u32) {
/// Port input data (y = 0..15)
IDR0: u1 = 0x0,
/// Port input data (y = 0..15)
IDR1: u1 = 0x0,
/// Port input data (y = 0..15)
IDR2: u1 = 0x0,
/// Port input data (y = 0..15)
IDR3: u1 = 0x0,
/// Port input data (y = 0..15)
IDR4: u1 = 0x0,
/// Port input data (y = 0..15)
IDR5: u1 = 0x0,
/// Port input data (y = 0..15)
IDR6: u1 = 0x0,
/// Port input data (y = 0..15)
IDR7: u1 = 0x0,
/// Port input data (y = 0..15)
IDR8: u1 = 0x0,
/// Port input data (y = 0..15)
IDR9: u1 = 0x0,
/// Port input data (y = 0..15)
IDR10: u1 = 0x0,
/// Port input data (y = 0..15)
IDR11: u1 = 0x0,
/// Port input data (y = 0..15)
IDR12: u1 = 0x0,
/// Port input data (y = 0..15)
IDR13: u1 = 0x0,
/// Port input data (y = 0..15)
IDR14: u1 = 0x0,
/// Port input data (y = 0..15)
IDR15: u1 = 0x0,
padding: u16 = 0,
}),
/// GPIO port output data register
/// offset: 0x14
ODR: mmio.Mmio(packed struct(u32) {
/// Port output data (y = 0..15)
ODR0: u1 = 0x0,
/// Port output data (y = 0..15)
ODR1: u1 = 0x0,
/// Port output data (y = 0..15)
ODR2: u1 = 0x0,
/// Port output data (y = 0..15)
ODR3: u1 = 0x0,
/// Port output data (y = 0..15)
ODR4: u1 = 0x0,
/// Port output data (y = 0..15)
ODR5: u1 = 0x0,
/// Port output data (y = 0..15)
ODR6: u1 = 0x0,
/// Port output data (y = 0..15)
ODR7: u1 = 0x0,
/// Port output data (y = 0..15)
ODR8: u1 = 0x0,
/// Port output data (y = 0..15)
ODR9: u1 = 0x0,
/// Port output data (y = 0..15)
ODR10: u1 = 0x0,
/// Port output data (y = 0..15)
ODR11: u1 = 0x0,
/// Port output data (y = 0..15)
ODR12: u1 = 0x0,
/// Port output data (y = 0..15)
ODR13: u1 = 0x0,
/// Port output data (y = 0..15)
ODR14: u1 = 0x0,
/// Port output data (y = 0..15)
ODR15: u1 = 0x0,
padding: u16 = 0,
}),
/// GPIO port bit set/reset register
/// offset: 0x18
BSRR: mmio.Mmio(packed struct(u32) {
/// Port x set bit y (y= 0..15)
BS0: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS1: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS2: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS3: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS4: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS5: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS6: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS7: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS8: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS9: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS10: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS11: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS12: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS13: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS14: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BS15: u1 = 0x0,
/// Port x set bit y (y= 0..15)
BR0: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR1: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR2: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR3: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR4: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR5: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR6: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR7: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR8: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR9: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR10: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR11: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR12: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR13: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR14: u1 = 0x0,
/// Port x reset bit y (y = 0..15)
BR15: u1 = 0x0,
}),
/// GPIO port configuration lock register
/// offset: 0x1c
LCKR: mmio.Mmio(packed struct(u32) {
/// Port x lock bit y (y= 0..15)
LCK0: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK1: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK2: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK3: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK4: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK5: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK6: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK7: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK8: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK9: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK10: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK11: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK12: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK13: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK14: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCK15: u1 = 0x0,
/// Port x lock bit y (y= 0..15)
LCKK: u1 = 0x0,
padding: u15 = 0,
}),
/// GPIO alternate function low register
/// offset: 0x20
AFRL: mmio.Mmio(packed struct(u32) {
/// Alternate function selection for port x bit y (y = 0..7)
AFRL0: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 0..7)
AFRL1: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 0..7)
AFRL2: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 0..7)
AFRL3: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 0..7)
AFRL4: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 0..7)
AFRL5: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 0..7)
AFRL6: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 0..7)
AFRL7: u4 = 0x0,
}),
/// GPIO alternate function high register
/// offset: 0x24
AFRH: mmio.Mmio(packed struct(u32) {
/// Alternate function selection for port x bit y (y = 8..15)
AFRH8: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 8..15)
AFRH9: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 8..15)
AFRH10: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 8..15)
AFRH11: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 8..15)
AFRH12: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 8..15)
AFRH13: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 8..15)
AFRH14: u4 = 0x0,
/// Alternate function selection for port x bit y (y = 8..15)
AFRH15: u4 = 0x0,
}),
/// GPIO port bit reset register
/// offset: 0x28
BRR: mmio.Mmio(packed struct(u32) {
/// Port Reset bit
BR0: u1 = 0x0,
/// Port Reset bit
BR1: u1 = 0x0,
/// Port Reset bit
BR2: u1 = 0x0,
/// Port Reset bit
BR3: u1 = 0x0,
/// Port Reset bit
BR4: u1 = 0x0,
/// Port Reset bit
BR5: u1 = 0x0,
/// Port Reset bit
BR6: u1 = 0x0,
/// Port Reset bit
BR7: u1 = 0x0,
/// Port Reset bit
BR8: u1 = 0x0,
/// Port Reset bit
BR9: u1 = 0x0,
/// Port Reset bit
BR10: u1 = 0x0,
/// Port Reset bit
BR11: u1 = 0x0,
/// Port Reset bit
BR12: u1 = 0x0,
/// Port Reset bit
BR13: u1 = 0x0,
/// Port Reset bit
BR14: u1 = 0x0,
/// Port Reset bit
BR15: u1 = 0x0,
padding: u16 = 0,
}),
};

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src/stm32g4/types/peripherals/I2C1.zig Normal file
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const microzig = @import("microzig");
const mmio = microzig.mmio;
const types = @import("../../types.zig");
/// Inter-integrated circuit
pub const I2C1 = extern struct {
/// Control register 1
/// offset: 0x00
CR1: mmio.Mmio(packed struct(u32) {
/// Peripheral enable
PE: u1 = 0x0,
/// TX Interrupt enable
TXIE: u1 = 0x0,
/// RX Interrupt enable
RXIE: u1 = 0x0,
/// Address match interrupt enable (slave only)
ADDRIE: u1 = 0x0,
/// Not acknowledge received interrupt enable
NACKIE: u1 = 0x0,
/// STOP detection Interrupt enable
STOPIE: u1 = 0x0,
/// Transfer Complete interrupt enable
TCIE: u1 = 0x0,
/// Error interrupts enable
ERRIE: u1 = 0x0,
/// Digital noise filter
DNF: u4 = 0x0,
/// Analog noise filter OFF
ANFOFF: u1 = 0x0,
reserved14: u1 = 0,
/// DMA transmission requests enable
TXDMAEN: u1 = 0x0,
/// DMA reception requests enable
RXDMAEN: u1 = 0x0,
/// Slave byte control
SBC: u1 = 0x0,
/// Clock stretching disable
NOSTRETCH: u1 = 0x0,
/// Wakeup from STOP enable
WUPEN: u1 = 0x0,
/// General call enable
GCEN: u1 = 0x0,
/// SMBus Host address enable
SMBHEN: u1 = 0x0,
/// SMBus Device Default address enable
SMBDEN: u1 = 0x0,
/// SMBUS alert enable
ALERTEN: u1 = 0x0,
/// PEC enable
PECEN: u1 = 0x0,
padding: u8 = 0,
}),
/// Control register 2
/// offset: 0x04
CR2: mmio.Mmio(packed struct(u32) {
/// Slave address bit (master mode)
SADD: u10 = 0x0,
/// Transfer direction (master mode)
RD_WRN: u1 = 0x0,
/// 10-bit addressing mode (master mode)
ADD10: u1 = 0x0,
/// 10-bit address header only read direction (master receiver mode)
HEAD10R: u1 = 0x0,
/// Start generation
START: u1 = 0x0,
/// Stop generation (master mode)
STOP: u1 = 0x0,
/// NACK generation (slave mode)
NACK: u1 = 0x0,
/// Number of bytes
NBYTES: u8 = 0x0,
/// NBYTES reload mode
RELOAD: u1 = 0x0,
/// Automatic end mode (master mode)
AUTOEND: u1 = 0x0,
/// Packet error checking byte
PECBYTE: u1 = 0x0,
padding: u5 = 0,
}),
/// Own address register 1
/// offset: 0x08
OAR1: mmio.Mmio(packed struct(u32) {
/// Interface address
OA1: u10 = 0x0,
/// Own Address 1 10-bit mode
OA1MODE: u1 = 0x0,
reserved15: u4 = 0,
/// Own Address 1 enable
OA1EN: u1 = 0x0,
padding: u16 = 0,
}),
/// Own address register 2
/// offset: 0x0c
OAR2: mmio.Mmio(packed struct(u32) {
reserved1: u1 = 0,
/// Interface address
OA2: u7 = 0x0,
/// Own Address 2 masks
OA2MSK: u3 = 0x0,
reserved15: u4 = 0,
/// Own Address 2 enable
OA2EN: u1 = 0x0,
padding: u16 = 0,
}),
/// Timing register
/// offset: 0x10
TIMINGR: mmio.Mmio(packed struct(u32) {
/// SCL low period (master mode)
SCLL: u8 = 0x0,
/// SCL high period (master mode)
SCLH: u8 = 0x0,
/// Data hold time
SDADEL: u4 = 0x0,
/// Data setup time
SCLDEL: u4 = 0x0,
reserved28: u4 = 0,
/// Timing prescaler
PRESC: u4 = 0x0,
}),
/// Status register 1
/// offset: 0x14
TIMEOUTR: mmio.Mmio(packed struct(u32) {
/// Bus timeout A
TIMEOUTA: u12 = 0x0,
/// Idle clock timeout detection
TIDLE: u1 = 0x0,
reserved15: u2 = 0,
/// Clock timeout enable
TIMOUTEN: u1 = 0x0,
/// Bus timeout B
TIMEOUTB: u12 = 0x0,
reserved31: u3 = 0,
/// Extended clock timeout enable
TEXTEN: u1 = 0x0,
}),
/// Interrupt and Status register
/// offset: 0x18
ISR: mmio.Mmio(packed struct(u32) {
/// Transmit data register empty (transmitters)
TXE: u1 = 0x1,
/// Transmit interrupt status (transmitters)
TXIS: u1 = 0x0,
/// Receive data register not empty (receivers)
RXNE: u1 = 0x0,
/// Address matched (slave mode)
ADDR: u1 = 0x0,
/// Not acknowledge received flag
NACKF: u1 = 0x0,
/// Stop detection flag
STOPF: u1 = 0x0,
/// Transfer Complete (master mode)
TC: u1 = 0x0,
/// Transfer Complete Reload
TCR: u1 = 0x0,
/// Bus error
BERR: u1 = 0x0,
/// Arbitration lost
ARLO: u1 = 0x0,
/// Overrun/Underrun (slave mode)
OVR: u1 = 0x0,
/// PEC Error in reception
PECERR: u1 = 0x0,
/// Timeout or t_low detection flag
TIMEOUT: u1 = 0x0,
/// SMBus alert
ALERT: u1 = 0x0,
reserved15: u1 = 0,
/// Bus busy
BUSY: u1 = 0x0,
/// Transfer direction (Slave mode)
DIR: u1 = 0x0,
/// Address match code (Slave mode)
ADDCODE: u7 = 0x0,
padding: u8 = 0,
}),
/// Interrupt clear register
/// offset: 0x1c
ICR: mmio.Mmio(packed struct(u32) {
reserved3: u3 = 0,
/// Address Matched flag clear
ADDRCF: u1 = 0x0,
/// Not Acknowledge flag clear
NACKCF: u1 = 0x0,
/// Stop detection flag clear
STOPCF: u1 = 0x0,
reserved8: u2 = 0,
/// Bus error flag clear
BERRCF: u1 = 0x0,
/// Arbitration lost flag clear
ARLOCF: u1 = 0x0,
/// Overrun/Underrun flag clear
OVRCF: u1 = 0x0,
/// PEC Error flag clear
PECCF: u1 = 0x0,
/// Timeout detection flag clear
TIMOUTCF: u1 = 0x0,
/// Alert flag clear
ALERTCF: u1 = 0x0,
padding: u18 = 0,
}),
/// PEC register
/// offset: 0x20
PECR: mmio.Mmio(packed struct(u32) {
/// Packet error checking register
PEC: u8 = 0x0,
padding: u24 = 0,
}),
/// Receive data register
/// offset: 0x24
RXDR: mmio.Mmio(packed struct(u32) {
/// 8-bit receive data
RXDATA: u8 = 0x0,
padding: u24 = 0,
}),
/// Transmit data register
/// offset: 0x28
TXDR: mmio.Mmio(packed struct(u32) {
/// 8-bit transmit data
TXDATA: u8 = 0x0,
padding: u24 = 0,
}),
};

47
src/stm32g4/types/peripherals/IWDG.zig Normal file
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const microzig = @import("microzig");
const mmio = microzig.mmio;
const types = @import("../../types.zig");
/// WinWATCHDOG
pub const IWDG = extern struct {
/// Key register
/// offset: 0x00
KR: mmio.Mmio(packed struct(u32) {
/// Key value (write only, read 0x0000)
KEY: u16 = 0x0,
padding: u16 = 0,
}),
/// Prescaler register
/// offset: 0x04
PR: mmio.Mmio(packed struct(u32) {
/// Prescaler divider
PR: u3 = 0x0,
padding: u29 = 0,
}),
/// Reload register
/// offset: 0x08
RLR: mmio.Mmio(packed struct(u32) {
/// Watchdog counter reload value
RL: u12 = 0xFFF,
padding: u20 = 0,
}),
/// Status register
/// offset: 0x0c
SR: mmio.Mmio(packed struct(u32) {
/// Watchdog prescaler value update
PVU: u1 = 0x0,
/// Watchdog counter reload value update
RVU: u1 = 0x0,
/// Watchdog counter window value update
WVU: u1 = 0x0,
padding: u29 = 0,
}),
/// Window register
/// offset: 0x10
WINR: mmio.Mmio(packed struct(u32) {
/// Watchdog counter window value
WIN: u12 = 0xFFF,
padding: u20 = 0,
}),
};

148
src/stm32g4/types/peripherals/LPTIM1.zig Normal file
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const microzig = @import("microzig");
const mmio = microzig.mmio;
const types = @import("../../types.zig");
/// Low power timer
pub const LPTIM1 = extern struct {
/// Interrupt and Status Register
/// offset: 0x00
ISR: mmio.Mmio(packed struct(u32) {
/// Compare match
CMPM: u1 = 0x0,
/// Autoreload match
ARRM: u1 = 0x0,
/// External trigger edge event
EXTTRIG: u1 = 0x0,
/// Compare register update OK
CMPOK: u1 = 0x0,
/// Autoreload register update OK
ARROK: u1 = 0x0,
/// Counter direction change down to up
UP: u1 = 0x0,
/// Counter direction change up to down
DOWN: u1 = 0x0,
padding: u25 = 0,
}),
/// Interrupt Clear Register
/// offset: 0x04
ICR: mmio.Mmio(packed struct(u32) {
/// compare match Clear Flag
CMPMCF: u1 = 0x0,
/// Autoreload match Clear Flag
ARRMCF: u1 = 0x0,
/// External trigger valid edge Clear Flag
EXTTRIGCF: u1 = 0x0,
/// Compare register update OK Clear Flag
CMPOKCF: u1 = 0x0,
/// Autoreload register update OK Clear Flag
ARROKCF: u1 = 0x0,
/// Direction change to UP Clear Flag
UPCF: u1 = 0x0,
/// Direction change to down Clear Flag
DOWNCF: u1 = 0x0,
padding: u25 = 0,
}),
/// Interrupt Enable Register
/// offset: 0x08
IER: mmio.Mmio(packed struct(u32) {
/// Compare match Interrupt Enable
CMPMIE: u1 = 0x0,
/// Autoreload match Interrupt Enable
ARRMIE: u1 = 0x0,
/// External trigger valid edge Interrupt Enable
EXTTRIGIE: u1 = 0x0,
/// Compare register update OK Interrupt Enable
CMPOKIE: u1 = 0x0,
/// Autoreload register update OK Interrupt Enable
ARROKIE: u1 = 0x0,
/// Direction change to UP Interrupt Enable
UPIE: u1 = 0x0,
/// Direction change to down Interrupt Enable
DOWNIE: u1 = 0x0,
padding: u25 = 0,
}),
/// Configuration Register
/// offset: 0x0c
CFGR: mmio.Mmio(packed struct(u32) {
/// Clock selector
CKSEL: u1 = 0x0,
/// Clock Polarity
CKPOL: u2 = 0x0,
/// Configurable digital filter for external clock
CKFLT: u2 = 0x0,
reserved6: u1 = 0,
/// Configurable digital filter for trigger
TRGFLT: u2 = 0x0,
reserved9: u1 = 0,
/// Clock prescaler
PRESC: u3 = 0x0,
reserved13: u1 = 0,
/// Trigger selector
TRIGSEL: u4 = 0x0,
/// Trigger enable and polarity
TRIGEN: u2 = 0x0,
/// Timeout enable
TIMOUT: u1 = 0x0,
/// Waveform shape
WAVE: u1 = 0x0,
/// Waveform shape polarity
WAVPOL: u1 = 0x0,
/// Registers update mode
PRELOAD: u1 = 0x0,
/// counter mode enabled
COUNTMODE: u1 = 0x0,
/// Encoder mode enable
ENC: u1 = 0x0,
padding: u7 = 0,
}),
/// Control Register
/// offset: 0x10
CR: mmio.Mmio(packed struct(u32) {
/// LPTIM Enable
ENABLE: u1 = 0x0,
/// LPTIM start in single mode
SNGSTRT: u1 = 0x0,
/// Timer start in continuous mode
CNTSTRT: u1 = 0x0,
/// COUNTRST
COUNTRST: u1 = 0x0,
/// RSTARE
RSTARE: u1 = 0x0,
padding: u27 = 0,
}),
/// Compare Register
/// offset: 0x14
CMP: mmio.Mmio(packed struct(u32) {
/// Compare value
CMP: u16 = 0x0,
padding: u16 = 0,
}),
/// Autoreload Register
/// offset: 0x18
ARR: mmio.Mmio(packed struct(u32) {
/// Auto reload value
ARR: u16 = 0x1,
padding: u16 = 0,
}),
/// Counter Register
/// offset: 0x1c
CNT: mmio.Mmio(packed struct(u32) {
/// Counter value
CNT: u16 = 0x0,
padding: u16 = 0,
}),
/// option register
/// offset: 0x20
OR: mmio.Mmio(packed struct(u32) {
/// IN1
IN1: u1 = 0x0,
/// IN2
IN2: u1 = 0x0,
/// IN1_2_1
IN1_2_1: u2 = 0x0,
/// IN2_2_1
IN2_2_1: u2 = 0x0,
padding: u26 = 0,
}),
};

262
src/stm32g4/types/peripherals/LPUART1.zig Normal file
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const microzig = @import("microzig");
const mmio = microzig.mmio;
const types = @import("../../types.zig");
/// Universal synchronous asynchronous receiver transmitter
pub const LPUART1 = extern struct {
/// Control register 1
/// offset: 0x00
CR1: mmio.Mmio(packed struct(u32) {
/// USART enable
UE: u1 = 0x0,
/// USART enable in Stop mode
UESM: u1 = 0x0,
/// Receiver enable
RE: u1 = 0x0,
/// Transmitter enable
TE: u1 = 0x0,
/// IDLE interrupt enable
IDLEIE: u1 = 0x0,
/// RXNE interrupt enable
RXNEIE: u1 = 0x0,
/// Transmission complete interrupt enable
TCIE: u1 = 0x0,
/// interrupt enable
TXEIE: u1 = 0x0,
/// PE interrupt enable
PEIE: u1 = 0x0,
/// Parity selection
PS: u1 = 0x0,
/// Parity control enable
PCE: u1 = 0x0,
/// Receiver wakeup method
WAKE: u1 = 0x0,
/// Word length
M0: u1 = 0x0,
/// Mute mode enable
MME: u1 = 0x0,
/// Character match interrupt enable
CMIE: u1 = 0x0,
reserved16: u1 = 0,
/// DEDT0
DEDT0: u1 = 0x0,
/// DEDT1
DEDT1: u1 = 0x0,
/// DEDT2
DEDT2: u1 = 0x0,
/// DEDT3
DEDT3: u1 = 0x0,
/// Driver Enable de-assertion time
DEDT4: u1 = 0x0,
/// DEAT0
DEAT0: u1 = 0x0,
/// DEAT1
DEAT1: u1 = 0x0,
/// DEAT2
DEAT2: u1 = 0x0,
/// DEAT3
DEAT3: u1 = 0x0,
/// Driver Enable assertion time
DEAT4: u1 = 0x0,
reserved28: u2 = 0,
/// Word length
M1: u1 = 0x0,
/// FIFOEN
FIFOEN: u1 = 0x0,
/// TXFEIE
TXFEIE: u1 = 0x0,
/// RXFFIE
RXFFIE: u1 = 0x0,
}),
/// Control register 2
/// offset: 0x04
CR2: mmio.Mmio(packed struct(u32) {
reserved4: u4 = 0,
/// 7-bit Address Detection/4-bit Address Detection
ADDM7: u1 = 0x0,
reserved12: u7 = 0,
/// STOP bits
STOP: u2 = 0x0,
reserved15: u1 = 0,
/// Swap TX/RX pins
SWAP: u1 = 0x0,
/// RX pin active level inversion
RXINV: u1 = 0x0,
/// TX pin active level inversion
TXINV: u1 = 0x0,
/// Binary data inversion
TAINV: u1 = 0x0,
/// Most significant bit first
MSBFIRST: u1 = 0x0,
reserved24: u4 = 0,
/// Address of the USART node
ADD0_3: u4 = 0x0,
/// Address of the USART node
ADD4_7: u4 = 0x0,
}),
/// Control register 3
/// offset: 0x08
CR3: mmio.Mmio(packed struct(u32) {
/// Error interrupt enable
EIE: u1 = 0x0,
reserved3: u2 = 0,
/// Half-duplex selection
HDSEL: u1 = 0x0,
reserved6: u2 = 0,
/// DMA enable receiver
DMAR: u1 = 0x0,
/// DMA enable transmitter
DMAT: u1 = 0x0,
/// RTS enable
RTSE: u1 = 0x0,
/// CTS enable
CTSE: u1 = 0x0,
/// CTS interrupt enable
CTSIE: u1 = 0x0,
reserved12: u1 = 0,
/// Overrun Disable
OVRDIS: u1 = 0x0,
/// DMA Disable on Reception Error
DDRE: u1 = 0x0,
/// Driver enable mode
DEM: u1 = 0x0,
/// Driver enable polarity selection
DEP: u1 = 0x0,
reserved20: u4 = 0,
/// Wakeup from Stop mode interrupt flag selection
WUS: u2 = 0x0,
/// Wakeup from Stop mode interrupt enable
WUFIE: u1 = 0x0,
/// TXFTIE
TXFTIE: u1 = 0x0,
reserved25: u1 = 0,
/// RXFTCFG
RXFTCFG: u3 = 0x0,
/// RXFTIE
RXFTIE: u1 = 0x0,
/// TXFTCFG
TXFTCFG: u3 = 0x0,
}),
/// Baud rate register
/// offset: 0x0c
BRR: mmio.Mmio(packed struct(u32) {
/// BRR
BRR: u20 = 0x0,
padding: u12 = 0,
}),
/// offset: 0x10
reserved16: [8]u8,
/// Request register
/// offset: 0x18
RQR: mmio.Mmio(packed struct(u32) {
reserved1: u1 = 0,
/// Send break request
SBKRQ: u1 = 0x0,
/// Mute mode request
MMRQ: u1 = 0x0,
/// Receive data flush request
RXFRQ: u1 = 0x0,
/// TXFRQ
TXFRQ: u1 = 0x0,
padding: u27 = 0,
}),
/// Interrupt & status register
/// offset: 0x1c
ISR: mmio.Mmio(packed struct(u32) {
/// PE
PE: u1 = 0x0,
/// FE
FE: u1 = 0x0,
/// NF
NF: u1 = 0x0,
/// ORE
ORE: u1 = 0x0,
/// IDLE
IDLE: u1 = 0x0,
/// RXNE
RXNE: u1 = 0x0,
/// TC
TC: u1 = 0x1,
/// TXE
TXE: u1 = 0x1,
reserved9: u1 = 0,
/// CTSIF
CTSIF: u1 = 0x0,
/// CTS
CTS: u1 = 0x0,
reserved16: u5 = 0,
/// BUSY
BUSY: u1 = 0x0,
/// CMF
CMF: u1 = 0x0,
/// SBKF
SBKF: u1 = 0x0,
/// RWU
RWU: u1 = 0x0,
/// WUF
WUF: u1 = 0x0,
/// TEACK
TEACK: u1 = 0x0,
/// REACK
REACK: u1 = 0x0,
/// TXFE
TXFE: u1 = 0x0,
/// RXFF
RXFF: u1 = 0x0,
reserved26: u1 = 0,
/// RXFT
RXFT: u1 = 0x0,
/// TXFT
TXFT: u1 = 0x0,
padding: u4 = 0,
}),
/// Interrupt flag clear register
/// offset: 0x20
ICR: mmio.Mmio(packed struct(u32) {
/// Parity error clear flag
PECF: u1 = 0x0,
/// Framing error clear flag
FECF: u1 = 0x0,
/// Noise detected clear flag
NCF: u1 = 0x0,
/// Overrun error clear flag
ORECF: u1 = 0x0,
/// Idle line detected clear flag
IDLECF: u1 = 0x0,
reserved6: u1 = 0,
/// Transmission complete clear flag
TCCF: u1 = 0x0,
reserved9: u2 = 0,
/// CTS clear flag
CTSCF: u1 = 0x0,
reserved17: u7 = 0,
/// Character match clear flag
CMCF: u1 = 0x0,
reserved20: u2 = 0,
/// Wakeup from Stop mode clear flag
WUCF: u1 = 0x0,
padding: u11 = 0,
}),
/// Receive data register
/// offset: 0x24
RDR: mmio.Mmio(packed struct(u32) {
/// Receive data value
RDR: u9 = 0x0,
padding: u23 = 0,
}),
/// Transmit data register
/// offset: 0x28
TDR: mmio.Mmio(packed struct(u32) {
/// Transmit data value
TDR: u9 = 0x0,
padding: u23 = 0,
}),
/// Prescaler register
/// offset: 0x2c
PRESC: mmio.Mmio(packed struct(u32) {
/// PRESCALER
PRESCALER: u4 = 0x0,
padding: u28 = 0,
}),
};

314
src/stm32g4/types/peripherals/OPAMP.zig Normal file
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const microzig = @import("microzig");
const mmio = microzig.mmio;
const types = @import("../../types.zig");
/// Operational amplifiers
pub const OPAMP = extern struct {
/// OPAMP1 control/status register
/// offset: 0x00
OPAMP1_CSR: mmio.Mmio(packed struct(u32) {
/// Operational amplifier Enable
OPAEN: u1 = 0x0,
/// FORCE_VP
FORCE_VP: u1 = 0x0,
/// VP_SEL
VP_SEL: u2 = 0x0,
/// USERTRIM
USERTRIM: u1 = 0x0,
/// VM_SEL
VM_SEL: u2 = 0x0,
/// OPAHSM
OPAHSM: u1 = 0x0,
/// OPAINTOEN
OPAINTOEN: u1 = 0x0,
reserved11: u2 = 0,
/// CALON
CALON: u1 = 0x0,
/// CALSEL
CALSEL: u2 = 0x0,
/// PGA_GAIN
PGA_GAIN: u5 = 0x0,
/// TRIMOFFSETP
TRIMOFFSETP: u5 = 0x0,
/// TRIMOFFSETN
TRIMOFFSETN: u5 = 0x0,
reserved30: u1 = 0,
/// CALOUT
CALOUT: u1 = 0x0,
/// LOCK
LOCK: u1 = 0x0,
}),
/// OPAMP2 control/status register
/// offset: 0x04
OPAMP2_CSR: mmio.Mmio(packed struct(u32) {
/// Operational amplifier Enable
OPAEN: u1 = 0x0,
/// FORCE_VP
FORCE_VP: u1 = 0x0,
/// VP_SEL
VP_SEL: u2 = 0x0,
/// USERTRIM
USERTRIM: u1 = 0x0,
/// VM_SEL
VM_SEL: u2 = 0x0,
/// OPAHSM
OPAHSM: u1 = 0x0,
/// OPAINTOEN
OPAINTOEN: u1 = 0x0,
reserved11: u2 = 0,
/// CALON
CALON: u1 = 0x0,
/// CALSEL
CALSEL: u2 = 0x0,
/// PGA_GAIN
PGA_GAIN: u5 = 0x0,
/// TRIMOFFSETP
TRIMOFFSETP: u5 = 0x0,
/// TRIMOFFSETN
TRIMOFFSETN: u5 = 0x0,
reserved30: u1 = 0,
/// CALOUT
CALOUT: u1 = 0x0,
/// LOCK
LOCK: u1 = 0x0,
}),
/// OPAMP3 control/status register
/// offset: 0x08
OPAMP3_CSR: mmio.Mmio(packed struct(u32) {
/// Operational amplifier Enable
OPAEN: u1 = 0x0,
/// FORCE_VP
FORCE_VP: u1 = 0x0,
/// VP_SEL
VP_SEL: u2 = 0x0,
/// USERTRIM
USERTRIM: u1 = 0x0,
/// VM_SEL
VM_SEL: u2 = 0x0,
/// OPAHSM
OPAHSM: u1 = 0x0,
/// OPAINTOEN
OPAINTOEN: u1 = 0x0,
reserved11: u2 = 0,
/// CALON
CALON: u1 = 0x0,
/// CALSEL
CALSEL: u2 = 0x0,
/// PGA_GAIN
PGA_GAIN: u5 = 0x0,
/// TRIMOFFSETP
TRIMOFFSETP: u5 = 0x0,
/// TRIMOFFSETN
TRIMOFFSETN: u5 = 0x0,
reserved30: u1 = 0,
/// CALOUT
CALOUT: u1 = 0x0,
/// LOCK
LOCK: u1 = 0x0,
}),
/// OPAMP4 control/status register
/// offset: 0x0c
OPAMP4_CSR: mmio.Mmio(packed struct(u32) {
/// Operational amplifier Enable
OPAEN: u1 = 0x0,
/// FORCE_VP
FORCE_VP: u1 = 0x0,
/// VP_SEL
VP_SEL: u2 = 0x0,
/// USERTRIM
USERTRIM: u1 = 0x0,
/// VM_SEL
VM_SEL: u2 = 0x0,
/// OPAHSM
OPAHSM: u1 = 0x0,
/// OPAINTOEN
OPAINTOEN: u1 = 0x0,
reserved11: u2 = 0,
/// CALON
CALON: u1 = 0x0,
/// CALSEL
CALSEL: u2 = 0x0,
/// PGA_GAIN
PGA_GAIN: u5 = 0x0,
/// TRIMOFFSETP
TRIMOFFSETP: u5 = 0x0,
/// TRIMOFFSETN
TRIMOFFSETN: u5 = 0x0,
reserved30: u1 = 0,
/// CALOUT
CALOUT: u1 = 0x0,
/// LOCK
LOCK: u1 = 0x0,
}),
/// OPAMP5 control/status register
/// offset: 0x10
OPAMP5_CSR: mmio.Mmio(packed struct(u32) {
/// Operational amplifier Enable
OPAEN: u1 = 0x0,
/// FORCE_VP
FORCE_VP: u1 = 0x0,
/// VP_SEL
VP_SEL: u2 = 0x0,
/// USERTRIM
USERTRIM: u1 = 0x0,
/// VM_SEL
VM_SEL: u2 = 0x0,
/// OPAHSM
OPAHSM: u1 = 0x0,
/// OPAINTOEN
OPAINTOEN: u1 = 0x0,
reserved11: u2 = 0,
/// CALON
CALON: u1 = 0x0,
/// CALSEL
CALSEL: u2 = 0x0,
/// PGA_GAIN
PGA_GAIN: u5 = 0x0,
/// TRIMOFFSETP
TRIMOFFSETP: u5 = 0x0,
/// TRIMOFFSETN
TRIMOFFSETN: u5 = 0x0,
reserved30: u1 = 0,
/// CALOUT
CALOUT: u1 = 0x0,
/// LOCK
LOCK: u1 = 0x0,
}),
/// OPAMP6 control/status register
/// offset: 0x14
OPAMP6_CSR: mmio.Mmio(packed struct(u32) {
/// Operational amplifier Enable
OPAEN: u1 = 0x0,
/// FORCE_VP
FORCE_VP: u1 = 0x0,
/// VP_SEL
VP_SEL: u2 = 0x0,
/// USERTRIM
USERTRIM: u1 = 0x0,
/// VM_SEL
VM_SEL: u2 = 0x0,
/// OPAHSM
OPAHSM: u1 = 0x0,
/// OPAINTOEN
OPAINTOEN: u1 = 0x0,
reserved11: u2 = 0,
/// CALON
CALON: u1 = 0x0,
/// CALSEL
CALSEL: u2 = 0x0,
/// PGA_GAIN
PGA_GAIN: u5 = 0x0,
/// TRIMOFFSETP
TRIMOFFSETP: u5 = 0x0,
/// TRIMOFFSETN
TRIMOFFSETN: u5 = 0x0,
reserved30: u1 = 0,
/// CALOUT
CALOUT: u1 = 0x0,
/// LOCK
LOCK: u1 = 0x0,
}),
/// OPAMP1 control/status register
/// offset: 0x18
OPAMP1_TCMR: mmio.Mmio(packed struct(u32) {
/// VMS_SEL
VMS_SEL: u1 = 0x0,
/// VPS_SEL
VPS_SEL: u2 = 0x0,
/// T1CM_EN
T1CM_EN: u1 = 0x0,
/// T8CM_EN
T8CM_EN: u1 = 0x0,
/// T20CM_EN
T20CM_EN: u1 = 0x0,
reserved31: u25 = 0,
/// LOCK
LOCK: u1 = 0x0,
}),
/// OPAMP2 control/status register
/// offset: 0x1c
OPAMP2_TCMR: mmio.Mmio(packed struct(u32) {
/// VMS_SEL
VMS_SEL: u1 = 0x0,
/// VPS_SEL
VPS_SEL: u2 = 0x0,
/// T1CM_EN
T1CM_EN: u1 = 0x0,
/// T8CM_EN
T8CM_EN: u1 = 0x0,
/// T20CM_EN
T20CM_EN: u1 = 0x0,
reserved31: u25 = 0,
/// LOCK
LOCK: u1 = 0x0,
}),
/// OPAMP3 control/status register
/// offset: 0x20
OPAMP3_TCMR: mmio.Mmio(packed struct(u32) {
/// VMS_SEL
VMS_SEL: u1 = 0x0,
/// VPS_SEL
VPS_SEL: u2 = 0x0,
/// T1CM_EN
T1CM_EN: u1 = 0x0,
/// T8CM_EN
T8CM_EN: u1 = 0x0,
/// T20CM_EN
T20CM_EN: u1 = 0x0,
reserved31: u25 = 0,
/// LOCK
LOCK: u1 = 0x0,
}),
/// OPAMP4 control/status register
/// offset: 0x24
OPAMP4_TCMR: mmio.Mmio(packed struct(u32) {
/// VMS_SEL
VMS_SEL: u1 = 0x0,
/// VPS_SEL
VPS_SEL: u2 = 0x0,
/// T1CM_EN
T1CM_EN: u1 = 0x0,
/// T8CM_EN
T8CM_EN: u1 = 0x0,
/// T20CM_EN
T20CM_EN: u1 = 0x0,
reserved31: u25 = 0,
/// LOCK
LOCK: u1 = 0x0,
}),
/// OPAMP5 control/status register
/// offset: 0x28
OPAMP5_TCMR: mmio.Mmio(packed struct(u32) {
/// VMS_SEL
VMS_SEL: u1 = 0x0,
/// VPS_SEL
VPS_SEL: u2 = 0x0,
/// T1CM_EN
T1CM_EN: u1 = 0x0,
/// T8CM_EN
T8CM_EN: u1 = 0x0,
/// T20CM_EN
T20CM_EN: u1 = 0x0,
reserved31: u25 = 0,
/// LOCK
LOCK: u1 = 0x0,
}),
/// OPAMP6 control/status register
/// offset: 0x2c
OPAMP6_TCMR: mmio.Mmio(packed struct(u32) {
/// VMS_SEL
VMS_SEL: u1 = 0x0,
/// VPS_SEL
VPS_SEL: u2 = 0x0,
/// T1CM_EN
T1CM_EN: u1 = 0x0,
/// T8CM_EN
T8CM_EN: u1 = 0x0,
/// T20CM_EN
T20CM_EN: u1 = 0x0,
reserved31: u25 = 0,
/// LOCK
LOCK: u1 = 0x0,
}),
};

799
src/stm32g4/types/peripherals/PWR.zig Normal file
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const microzig = @import("microzig");
const mmio = microzig.mmio;
const types = @import("../../types.zig");
/// Power control
pub const PWR = extern struct {
/// Power control register 1
/// offset: 0x00
PWR_CR1: mmio.Mmio(packed struct(u32) {
/// Low-power mode selection
LPMS: enum(u3) {
/// Stop 0 mode
B_0x0 = 0x0,
/// Stop 1 mode
B_0x1 = 0x1,
/// Standby mode
B_0x3 = 0x3,
_,
} = .B_0x0,
/// FPD_STOP
FPD_STOP: u1 = 0x0,
reserved8: u4 = 0,
/// Disable backup domain write protection
DBP: enum(u1) {
/// Access to RTC and Backup registers disabled
B_0x0 = 0x0,
/// Access to RTC and Backup registers enabled
B_0x1 = 0x1,
} = .B_0x0,
/// Voltage scaling range selection
VOS: enum(u2) {
/// Cannot be written (forbidden by hardware)
B_0x0 = 0x0,
/// Range 1
B_0x1 = 0x1,
/// Range 2
B_0x2 = 0x2,
/// Cannot be written (forbidden by hardware)
B_0x3 = 0x3,
} = .B_0x1,
reserved14: u3 = 0,
/// Low-power run
LPR: u1 = 0x0,
padding: u17 = 0,
}),
/// Power control register 2
/// offset: 0x04
PWR_CR2: mmio.Mmio(packed struct(u32) {
/// Programmable voltage detector enable
PVDE: enum(u1) {
/// Programmable voltage detector disable.
B_0x0 = 0x0,
/// Programmable voltage detector enable.
B_0x1 = 0x1,
} = .B_0x0,
/// Programmable voltage detector level selection.
PVDLS: enum(u3) {
/// V<sub>PVD0</sub> PVD threshold 0
B_0x0 = 0x0,
/// V<sub>PVD1</sub> PVD threshold 1
B_0x1 = 0x1,
/// V<sub>PVD2</sub> PVD threshold 2
B_0x2 = 0x2,
/// V<sub>PVD3</sub> PVD threshold 3
B_0x3 = 0x3,
/// V<sub>PVD4</sub> PVD threshold 4
B_0x4 = 0x4,
/// V<sub>PVD5</sub> PVD threshold 5
B_0x5 = 0x5,
/// V<sub>PVD6</sub> PVD threshold 6
B_0x6 = 0x6,
/// External input analog voltage PVD_IN (compared internally to V<sub>REFINT</sub>)
B_0x7 = 0x7,
} = .B_0x0,
reserved6: u2 = 0,
/// Peripheral voltage monitoring 3 enable: V<sub>DDA</sub> vs. ADC/COMP min voltage 1.62V
PVMEN1: enum(u1) {
/// PVM1 (V<sub>DDA</sub> monitoring vs. 1.62V threshold) disable.
B_0x0 = 0x0,
/// PVM1 (V<sub>DDA</sub> monitoring vs. 1.62V threshold) enable.
B_0x1 = 0x1,
} = .B_0x0,
/// Peripheral voltage monitoring 4 enable: V<sub>DDA</sub> vs. DAC 1MSPS /DAC 15MSPS min voltage.
PVMEN2: enum(u1) {
/// PVM2 (V<sub>DDA</sub> monitoring vs. 1.8 V threshold) disable.
B_0x0 = 0x0,
/// PVM2 (V<sub>DDA</sub> monitoring vs. 1.8 V threshold) enable.
B_0x1 = 0x1,
} = .B_0x0,
padding: u24 = 0,
}),
/// Power control register 3
/// offset: 0x08
PWR_CR3: mmio.Mmio(packed struct(u32) {
/// Enable Wakeup pin WKUP1
EWUP1: u1 = 0x0,
/// Enable Wakeup pin WKUP2
EWUP2: u1 = 0x0,
/// Enable Wakeup pin WKUP3
EWUP3: u1 = 0x0,
/// Enable Wakeup pin WKUP4
EWUP4: u1 = 0x0,
/// Enable Wakeup pin WKUP5
EWUP5: u1 = 0x0,
reserved8: u3 = 0,
/// SRAM2 retention in Standby mode
RRS: enum(u1) {
/// SRAM2 is powered off in Standby mode (SRAM2 content is lost).
B_0x0 = 0x0,
/// SRAM2 is powered by the low-power regulator in Standby mode (SRAM2 content is kept).
B_0x1 = 0x1,
} = .B_0x0,
reserved10: u1 = 0,
/// Apply pull-up and pull-down configuration
APC: u1 = 0x0,
reserved13: u2 = 0,
/// UCPD1_STDBY USB Type-C and Power Delivery standby mode.
UCPD1_STDBY: enum(u1) {
/// Write 0 immediately after standby exit when using UCPD1, (and before writing any UCPD1 registers).
B_0x0 = 0x0,
/// Write 1 just before entering standby when using UCPD1.
B_0x1 = 0x1,
} = .B_0x0,
/// USB Type-C and Power Delivery Dead Battery disable.
UCPD1_DBDIS: enum(u1) {
/// Enable USB Type-C dead battery pull-down behavior on UCPD1_CC1 and UCPD1_CC2 pins.
B_0x0 = 0x0,
/// Disable USB Type-C dead battery pull-down behavior on UCPD1_CC1 and UCPD1_CC2 pins.
B_0x1 = 0x1,
} = .B_0x0,
/// Enable internal wakeup line
EIWUL: enum(u1) {
/// Internal wakeup line disable.
B_0x0 = 0x0,
/// Internal wakeup line enable.
B_0x1 = 0x1,
} = .B_0x1,
padding: u16 = 0,
}),
/// Power control register 4
/// offset: 0x0c
PWR_CR4: mmio.Mmio(packed struct(u32) {
/// Wakeup pin WKUP1 polarity
WP1: enum(u1) {
/// Detection on high level (rising edge)
B_0x0 = 0x0,
/// Detection on low level (falling edge)
B_0x1 = 0x1,
} = .B_0x0,
/// Wakeup pin WKUP2 polarity
WP2: enum(u1) {
/// Detection on high level (rising edge)
B_0x0 = 0x0,
/// Detection on low level (falling edge)
B_0x1 = 0x1,
} = .B_0x0,
/// Wakeup pin WKUP3 polarity
WP3: enum(u1) {
/// Detection on high level (rising edge)
B_0x0 = 0x0,
/// Detection on low level (falling edge)
B_0x1 = 0x1,
} = .B_0x0,
/// Wakeup pin WKUP4 polarity
WP4: enum(u1) {
/// Detection on high level (rising edge)
B_0x0 = 0x0,
/// Detection on low level (falling edge)
B_0x1 = 0x1,
} = .B_0x0,
/// Wakeup pin WKUP5 polarity
WP5: enum(u1) {
/// Detection on high level (rising edge)
B_0x0 = 0x0,
/// Detection on low level (falling edge)
B_0x1 = 0x1,
} = .B_0x0,
reserved8: u3 = 0,
/// V<sub>BAT</sub> battery charging enable
VBE: enum(u1) {
/// V<sub>BAT</sub> battery charging disable
B_0x0 = 0x0,
/// V<sub>BAT</sub> battery charging enable
B_0x1 = 0x1,
} = .B_0x0,
/// V<sub>BAT</sub> battery charging resistor selection
VBRS: enum(u1) {
/// Charge V<sub>BAT</sub> through a 5 kOhms resistor
B_0x0 = 0x0,
/// Charge V<sub>BAT</sub> through a 1.5 kOhms resistor
B_0x1 = 0x1,
} = .B_0x0,
padding: u22 = 0,
}),
/// Power status register 1
/// offset: 0x10
PWR_SR1: mmio.Mmio(packed struct(u32) {
/// Wakeup flag 1
WUF1: u1 = 0x0,
/// Wakeup flag 2
WUF2: u1 = 0x0,
/// Wakeup flag 3
WUF3: u1 = 0x0,
/// Wakeup flag 4
WUF4: u1 = 0x0,
/// Wakeup flag 5
WUF5: u1 = 0x0,
reserved8: u3 = 0,
/// Standby flag
SBF: enum(u1) {
/// The device did not enter the Standby mode
B_0x0 = 0x0,
/// The device entered the Standby mode
B_0x1 = 0x1,
} = .B_0x0,
reserved15: u6 = 0,
/// Wakeup flag internal
WUFI: u1 = 0x0,
padding: u16 = 0,
}),
/// Power status register 2
/// offset: 0x14
PWR_SR2: mmio.Mmio(packed struct(u32) {
reserved8: u8 = 0,
/// Low-power regulator started
REGLPS: enum(u1) {
/// The low-power regulator is not ready
B_0x0 = 0x0,
/// The low-power regulator is ready
B_0x1 = 0x1,
} = .B_0x0,
/// Low-power regulator flag
REGLPF: enum(u1) {
/// The regulator is ready in main mode (MR)
B_0x0 = 0x0,
/// The regulator is in low-power mode (LPR)
B_0x1 = 0x1,
} = .B_0x0,
/// Voltage scaling flag
VOSF: enum(u1) {
/// The regulator is ready in the selected voltage range
B_0x0 = 0x0,
/// The regulator output voltage is changing to the required voltage level
B_0x1 = 0x1,
} = .B_0x0,
/// Programmable voltage detector output
PVDO: enum(u1) {
/// V<sub>DD</sub> is above the selected PVD threshold
B_0x0 = 0x0,
/// V<sub>DD</sub> is below the selected PVD threshold
B_0x1 = 0x1,
} = .B_0x0,
reserved14: u2 = 0,
/// Peripheral voltage monitoring output: V<sub>DDA</sub> vs. 1.62 V
PVMO1: enum(u1) {
/// V<sub>DDA</sub> voltage is above PVM1 threshold (around 1.62 V).
B_0x0 = 0x0,
/// V<sub>DDA</sub> voltage is below PVM1 threshold (around 1.62 V).
B_0x1 = 0x1,
} = .B_0x0,
/// Peripheral voltage monitoring output: V<sub>DDA</sub> vs. 1.8 V
PVMO2: enum(u1) {
/// V<sub>DDA</sub> voltage is above PVM2 threshold (around 1.8 V).
B_0x0 = 0x0,
/// V<sub>DDA</sub> voltage is below PVM2 threshold (around 1.8 V).
B_0x1 = 0x1,
} = .B_0x0,
padding: u16 = 0,
}),
/// Power status clear register
/// offset: 0x18
PWR_SCR: mmio.Mmio(packed struct(u32) {
/// Clear wakeup flag 1
CWUF1: u1 = 0x0,
/// Clear wakeup flag 2
CWUF2: u1 = 0x0,
/// Clear wakeup flag 3
CWUF3: u1 = 0x0,
/// Clear wakeup flag 4
CWUF4: u1 = 0x0,
/// Clear wakeup flag 5
CWUF5: u1 = 0x0,
reserved8: u3 = 0,
/// Clear standby flag
CSBF: u1 = 0x0,
padding: u23 = 0,
}),
/// offset: 0x1c
reserved28: [4]u8,
/// Power Port A pull-up control register
/// offset: 0x20
PWR_PUCRA: mmio.Mmio(packed struct(u32) {
/// Port A pull-up bit y (y=0..13)
PU0: u1 = 0x0,
/// Port A pull-up bit y (y=0..13)
PU1: u1 = 0x0,
/// Port A pull-up bit y (y=0..13)
PU2: u1 = 0x0,
/// Port A pull-up bit y (y=0..13)
PU3: u1 = 0x0,
/// Port A pull-up bit y (y=0..13)
PU4: u1 = 0x0,
/// Port A pull-up bit y (y=0..13)
PU5: u1 = 0x0,
/// Port A pull-up bit y (y=0..13)
PU6: u1 = 0x0,
/// Port A pull-up bit y (y=0..13)
PU7: u1 = 0x0,
/// Port A pull-up bit y (y=0..13)
PU8: u1 = 0x0,
/// Port A pull-up bit y (y=0..13)
PU9: u1 = 0x0,
/// Port A pull-up bit y (y=0..13)
PU10: u1 = 0x0,
/// Port A pull-up bit y (y=0..13)
PU11: u1 = 0x0,
/// Port A pull-up bit y (y=0..13)
PU12: u1 = 0x0,
/// Port A pull-up bit y (y=0..13)
PU13: u1 = 0x0,
reserved15: u1 = 0,
/// Port A pull-up bit 15
PU15: u1 = 0x0,
padding: u16 = 0,
}),
/// Power Port A pull-down control register
/// offset: 0x24
PWR_PDCRA: mmio.Mmio(packed struct(u32) {
/// Port A pull-down bit y (y=0..12)
PD0: u1 = 0x0,
/// Port A pull-down bit y (y=0..12)
PD1: u1 = 0x0,
/// Port A pull-down bit y (y=0..12)
PD2: u1 = 0x0,
/// Port A pull-down bit y (y=0..12)
PD3: u1 = 0x0,
/// Port A pull-down bit y (y=0..12)
PD4: u1 = 0x0,
/// Port A pull-down bit y (y=0..12)
PD5: u1 = 0x0,
/// Port A pull-down bit y (y=0..12)
PD6: u1 = 0x0,
/// Port A pull-down bit y (y=0..12)
PD7: u1 = 0x0,
/// Port A pull-down bit y (y=0..12)
PD8: u1 = 0x0,
/// Port A pull-down bit y (y=0..12)
PD9: u1 = 0x0,
/// Port A pull-down bit y (y=0..12)
PD10: u1 = 0x0,
/// Port A pull-down bit y (y=0..12)
PD11: u1 = 0x0,
/// Port A pull-down bit y (y=0..12)
PD12: u1 = 0x0,
reserved14: u1 = 0,
/// Port A pull-down bit 14
PD14: u1 = 0x0,
padding: u17 = 0,
}),
/// Power Port B pull-up control register
/// offset: 0x28
PWR_PUCRB: mmio.Mmio(packed struct(u32) {
/// Port B pull-up bit y (y=0..15)
PU0: u1 = 0x0,
/// Port B pull-up bit y (y=0..15)
PU1: u1 = 0x0,
/// Port B pull-up bit y (y=0..15)
PU2: u1 = 0x0,
/// Port B pull-up bit y (y=0..15)
PU3: u1 = 0x0,
/// Port B pull-up bit y (y=0..15)
PU4: u1 = 0x0,
/// Port B pull-up bit y (y=0..15)
PU5: u1 = 0x0,
/// Port B pull-up bit y (y=0..15)
PU6: u1 = 0x0,
/// Port B pull-up bit y (y=0..15)
PU7: u1 = 0x0,
/// Port B pull-up bit y (y=0..15)
PU8: u1 = 0x0,
/// Port B pull-up bit y (y=0..15)
PU9: u1 = 0x0,
/// Port B pull-up bit y (y=0..15)
PU10: u1 = 0x0,
/// Port B pull-up bit y (y=0..15)
PU11: u1 = 0x0,
/// Port B pull-up bit y (y=0..15)
PU12: u1 = 0x0,
/// Port B pull-up bit y (y=0..15)
PU13: u1 = 0x0,
/// Port B pull-up bit y (y=0..15)
PU14: u1 = 0x0,
/// Port B pull-up bit y (y=0..15)
PU15: u1 = 0x0,
padding: u16 = 0,
}),
/// Power Port B pull-down control register
/// offset: 0x2c
PWR_PDCRB: mmio.Mmio(packed struct(u32) {
/// Port B pull-down bit y (y=0..3)
PD0: u1 = 0x0,
/// Port B pull-down bit y (y=0..3)
PD1: u1 = 0x0,
/// Port B pull-down bit y (y=0..3)
PD2: u1 = 0x0,
/// Port B pull-down bit y (y=0..3)
PD3: u1 = 0x0,
reserved5: u1 = 0,
/// Port B pull-down bit y (y=5..15)
PD5: u1 = 0x0,
/// Port B pull-down bit y (y=5..15)
PD6: u1 = 0x0,
/// Port B pull-down bit y (y=5..15)
PD7: u1 = 0x0,
/// Port B pull-down bit y (y=5..15)
PD8: u1 = 0x0,
/// Port B pull-down bit y (y=5..15)
PD9: u1 = 0x0,
/// Port B pull-down bit y (y=5..15)
PD10: u1 = 0x0,
/// Port B pull-down bit y (y=5..15)
PD11: u1 = 0x0,
/// Port B pull-down bit y (y=5..15)
PD12: u1 = 0x0,
/// Port B pull-down bit y (y=5..15)
PD13: u1 = 0x0,
/// Port B pull-down bit y (y=5..15)
PD14: u1 = 0x0,
/// Port B pull-down bit y (y=5..15)
PD15: u1 = 0x0,
padding: u16 = 0,
}),
/// Power Port C pull-up control register
/// offset: 0x30
PWR_PUCRC: mmio.Mmio(packed struct(u32) {
/// Port C pull-up bit y (y=0..15)
PU0: u1 = 0x0,
/// Port C pull-up bit y (y=0..15)
PU1: u1 = 0x0,
/// Port C pull-up bit y (y=0..15)
PU2: u1 = 0x0,
/// Port C pull-up bit y (y=0..15)
PU3: u1 = 0x0,
/// Port C pull-up bit y (y=0..15)
PU4: u1 = 0x0,
/// Port C pull-up bit y (y=0..15)
PU5: u1 = 0x0,
/// Port C pull-up bit y (y=0..15)
PU6: u1 = 0x0,
/// Port C pull-up bit y (y=0..15)
PU7: u1 = 0x0,
/// Port C pull-up bit y (y=0..15)
PU8: u1 = 0x0,
/// Port C pull-up bit y (y=0..15)
PU9: u1 = 0x0,
/// Port C pull-up bit y (y=0..15)
PU10: u1 = 0x0,
/// Port C pull-up bit y (y=0..15)
PU11: u1 = 0x0,
/// Port C pull-up bit y (y=0..15)
PU12: u1 = 0x0,
/// Port C pull-up bit y (y=0..15)
PU13: u1 = 0x0,
/// Port C pull-up bit y (y=0..15)
PU14: u1 = 0x0,
/// Port C pull-up bit y (y=0..15)
PU15: u1 = 0x0,
padding: u16 = 0,
}),
/// Power Port C pull-down control register
/// offset: 0x34
PWR_PDCRC: mmio.Mmio(packed struct(u32) {
/// Port C pull-down bit y (y=0..15)
PD0: u1 = 0x0,
/// Port C pull-down bit y (y=0..15)
PD1: u1 = 0x0,
/// Port C pull-down bit y (y=0..15)
PD2: u1 = 0x0,
/// Port C pull-down bit y (y=0..15)
PD3: u1 = 0x0,
/// Port C pull-down bit y (y=0..15)
PD4: u1 = 0x0,
/// Port C pull-down bit y (y=0..15)
PD5: u1 = 0x0,
/// Port C pull-down bit y (y=0..15)
PD6: u1 = 0x0,
/// Port C pull-down bit y (y=0..15)
PD7: u1 = 0x0,
/// Port C pull-down bit y (y=0..15)
PD8: u1 = 0x0,
/// Port C pull-down bit y (y=0..15)
PD9: u1 = 0x0,
/// Port C pull-down bit y (y=0..15)
PD10: u1 = 0x0,
/// Port C pull-down bit y (y=0..15)
PD11: u1 = 0x0,
/// Port C pull-down bit y (y=0..15)
PD12: u1 = 0x0,
/// Port C pull-down bit y (y=0..15)
PD13: u1 = 0x0,
/// Port C pull-down bit y (y=0..15)
PD14: u1 = 0x0,
/// Port C pull-down bit y (y=0..15)
PD15: u1 = 0x0,
padding: u16 = 0,
}),
/// Power Port D pull-up control register
/// offset: 0x38
PWR_PUCRD: mmio.Mmio(packed struct(u32) {
/// Port D pull-up bit y (y=0..15)
PU0: u1 = 0x0,
/// Port D pull-up bit y (y=0..15)
PU1: u1 = 0x0,
/// Port D pull-up bit y (y=0..15)
PU2: u1 = 0x0,
/// Port D pull-up bit y (y=0..15)
PU3: u1 = 0x0,
/// Port D pull-up bit y (y=0..15)
PU4: u1 = 0x0,
/// Port D pull-up bit y (y=0..15)
PU5: u1 = 0x0,
/// Port D pull-up bit y (y=0..15)
PU6: u1 = 0x0,
/// Port D pull-up bit y (y=0..15)
PU7: u1 = 0x0,
/// Port D pull-up bit y (y=0..15)
PU8: u1 = 0x0,
/// Port D pull-up bit y (y=0..15)
PU9: u1 = 0x0,
/// Port D pull-up bit y (y=0..15)
PU10: u1 = 0x0,
/// Port D pull-up bit y (y=0..15)
PU11: u1 = 0x0,
/// Port D pull-up bit y (y=0..15)
PU12: u1 = 0x0,
/// Port D pull-up bit y (y=0..15)
PU13: u1 = 0x0,
/// Port D pull-up bit y (y=0..15)
PU14: u1 = 0x0,
/// Port D pull-up bit y (y=0..15)
PU15: u1 = 0x0,
padding: u16 = 0,
}),
/// Power Port D pull-down control register
/// offset: 0x3c
PWR_PDCRD: mmio.Mmio(packed struct(u32) {
/// Port D pull-down bit y (y=0..15)
PD0: u1 = 0x0,
/// Port D pull-down bit y (y=0..15)
PD1: u1 = 0x0,
/// Port D pull-down bit y (y=0..15)
PD2: u1 = 0x0,
/// Port D pull-down bit y (y=0..15)
PD3: u1 = 0x0,
/// Port D pull-down bit y (y=0..15)
PD4: u1 = 0x0,
/// Port D pull-down bit y (y=0..15)
PD5: u1 = 0x0,
/// Port D pull-down bit y (y=0..15)
PD6: u1 = 0x0,
/// Port D pull-down bit y (y=0..15)
PD7: u1 = 0x0,
/// Port D pull-down bit y (y=0..15)
PD8: u1 = 0x0,
/// Port D pull-down bit y (y=0..15)
PD9: u1 = 0x0,
/// Port D pull-down bit y (y=0..15)
PD10: u1 = 0x0,
/// Port D pull-down bit y (y=0..15)
PD11: u1 = 0x0,
/// Port D pull-down bit y (y=0..15)
PD12: u1 = 0x0,
/// Port D pull-down bit y (y=0..15)
PD13: u1 = 0x0,
/// Port D pull-down bit y (y=0..15)
PD14: u1 = 0x0,
/// Port D pull-down bit y (y=0..15)
PD15: u1 = 0x0,
padding: u16 = 0,
}),
/// Power Port E pull-up control register
/// offset: 0x40
PWR_PUCRE: mmio.Mmio(packed struct(u32) {
/// Port E pull-up bit y (y=0..15)
PU0: u1 = 0x0,
/// Port E pull-up bit y (y=0..15)
PU1: u1 = 0x0,
/// Port E pull-up bit y (y=0..15)
PU2: u1 = 0x0,
/// Port E pull-up bit y (y=0..15)
PU3: u1 = 0x0,
/// Port E pull-up bit y (y=0..15)
PU4: u1 = 0x0,
/// Port E pull-up bit y (y=0..15)
PU5: u1 = 0x0,
/// Port E pull-up bit y (y=0..15)
PU6: u1 = 0x0,
/// Port E pull-up bit y (y=0..15)
PU7: u1 = 0x0,
/// Port E pull-up bit y (y=0..15)
PU8: u1 = 0x0,
/// Port E pull-up bit y (y=0..15)
PU9: u1 = 0x0,
/// Port E pull-up bit y (y=0..15)
PU10: u1 = 0x0,
/// Port E pull-up bit y (y=0..15)
PU11: u1 = 0x0,
/// Port E pull-up bit y (y=0..15)
PU12: u1 = 0x0,
/// Port E pull-up bit y (y=0..15)
PU13: u1 = 0x0,
/// Port E pull-up bit y (y=0..15)
PU14: u1 = 0x0,
/// Port E pull-up bit y (y=0..15)
PU15: u1 = 0x0,
padding: u16 = 0,
}),
/// Power Port E pull-down control register
/// offset: 0x44
PWR_PDCRE: mmio.Mmio(packed struct(u32) {
/// Port E pull-down bit y (y=0..15)
PD0: u1 = 0x0,
/// Port E pull-down bit y (y=0..15)
PD1: u1 = 0x0,
/// Port E pull-down bit y (y=0..15)
PD2: u1 = 0x0,
/// Port E pull-down bit y (y=0..15)
PD3: u1 = 0x0,
/// Port E pull-down bit y (y=0..15)
PD4: u1 = 0x0,
/// Port E pull-down bit y (y=0..15)
PD5: u1 = 0x0,
/// Port E pull-down bit y (y=0..15)
PD6: u1 = 0x0,
/// Port E pull-down bit y (y=0..15)
PD7: u1 = 0x0,
/// Port E pull-down bit y (y=0..15)
PD8: u1 = 0x0,
/// Port E pull-down bit y (y=0..15)
PD9: u1 = 0x0,
/// Port E pull-down bit y (y=0..15)
PD10: u1 = 0x0,
/// Port E pull-down bit y (y=0..15)
PD11: u1 = 0x0,
/// Port E pull-down bit y (y=0..15)
PD12: u1 = 0x0,
/// Port E pull-down bit y (y=0..15)
PD13: u1 = 0x0,
/// Port E pull-down bit y (y=0..15)
PD14: u1 = 0x0,
/// Port E pull-down bit y (y=0..15)
PD15: u1 = 0x0,
padding: u16 = 0,
}),
/// Power Port F pull-up control register
/// offset: 0x48
PWR_PUCRF: mmio.Mmio(packed struct(u32) {
/// Port F pull-up bit y (y=0..15)
PU0: u1 = 0x0,
/// Port F pull-up bit y (y=0..15)
PU1: u1 = 0x0,
/// Port F pull-up bit y (y=0..15)
PU2: u1 = 0x0,
/// Port F pull-up bit y (y=0..15)
PU3: u1 = 0x0,
/// Port F pull-up bit y (y=0..15)
PU4: u1 = 0x0,
/// Port F pull-up bit y (y=0..15)
PU5: u1 = 0x0,
/// Port F pull-up bit y (y=0..15)
PU6: u1 = 0x0,
/// Port F pull-up bit y (y=0..15)
PU7: u1 = 0x0,
/// Port F pull-up bit y (y=0..15)
PU8: u1 = 0x0,
/// Port F pull-up bit y (y=0..15)
PU9: u1 = 0x0,
/// Port F pull-up bit y (y=0..15)
PU10: u1 = 0x0,
/// Port F pull-up bit y (y=0..15)
PU11: u1 = 0x0,
/// Port F pull-up bit y (y=0..15)
PU12: u1 = 0x0,
/// Port F pull-up bit y (y=0..15)
PU13: u1 = 0x0,
/// Port F pull-up bit y (y=0..15)
PU14: u1 = 0x0,
/// Port F pull-up bit y (y=0..15)
PU15: u1 = 0x0,
padding: u16 = 0,
}),
/// Power Port F pull-down control register
/// offset: 0x4c
PWR_PDCRF: mmio.Mmio(packed struct(u32) {
/// Port F pull-down bit y (y=0..15)
PD0: u1 = 0x0,
/// Port F pull-down bit y (y=0..15)
PD1: u1 = 0x0,
/// Port F pull-down bit y (y=0..15)
PD2: u1 = 0x0,
/// Port F pull-down bit y (y=0..15)
PD3: u1 = 0x0,
/// Port F pull-down bit y (y=0..15)
PD4: u1 = 0x0,
/// Port F pull-down bit y (y=0..15)
PD5: u1 = 0x0,
/// Port F pull-down bit y (y=0..15)
PD6: u1 = 0x0,
/// Port F pull-down bit y (y=0..15)
PD7: u1 = 0x0,
/// Port F pull-down bit y (y=0..15)
PD8: u1 = 0x0,
/// Port F pull-down bit y (y=0..15)
PD9: u1 = 0x0,
/// Port F pull-down bit y (y=0..15)
PD10: u1 = 0x0,
/// Port F pull-down bit y (y=0..15)
PD11: u1 = 0x0,
/// Port F pull-down bit y (y=0..15)
PD12: u1 = 0x0,
/// Port F pull-down bit y (y=0..15)
PD13: u1 = 0x0,
/// Port F pull-down bit y (y=0..15)
PD14: u1 = 0x0,
/// Port F pull-down bit y (y=0..15)
PD15: u1 = 0x0,
padding: u16 = 0,
}),
/// Power Port G pull-up control register
/// offset: 0x50
PWR_PUCRG: mmio.Mmio(packed struct(u32) {
/// Port G pull-up bit y (y=0..10)
PU0: u1 = 0x0,
/// Port G pull-up bit y (y=0..10)
PU1: u1 = 0x0,
/// Port G pull-up bit y (y=0..10)
PU2: u1 = 0x0,
/// Port G pull-up bit y (y=0..10)
PU3: u1 = 0x0,
/// Port G pull-up bit y (y=0..10)
PU4: u1 = 0x0,
/// Port G pull-up bit y (y=0..10)
PU5: u1 = 0x0,
/// Port G pull-up bit y (y=0..10)
PU6: u1 = 0x0,
/// Port G pull-up bit y (y=0..10)
PU7: u1 = 0x0,
/// Port G pull-up bit y (y=0..10)
PU8: u1 = 0x0,
/// Port G pull-up bit y (y=0..10)
PU9: u1 = 0x0,
/// Port G pull-up bit y (y=0..10)
PU10: u1 = 0x0,
padding: u21 = 0,
}),
/// Power Port G pull-down control register
/// offset: 0x54
PWR_PDCRG: mmio.Mmio(packed struct(u32) {
/// Port G pull-down bit y (y=0..10)
PD0: u1 = 0x0,
/// Port G pull-down bit y (y=0..10)
PD1: u1 = 0x0,
/// Port G pull-down bit y (y=0..10)
PD2: u1 = 0x0,
/// Port G pull-down bit y (y=0..10)
PD3: u1 = 0x0,
/// Port G pull-down bit y (y=0..10)
PD4: u1 = 0x0,
/// Port G pull-down bit y (y=0..10)
PD5: u1 = 0x0,
/// Port G pull-down bit y (y=0..10)
PD6: u1 = 0x0,
/// Port G pull-down bit y (y=0..10)
PD7: u1 = 0x0,
/// Port G pull-down bit y (y=0..10)
PD8: u1 = 0x0,
/// Port G pull-down bit y (y=0..10)
PD9: u1 = 0x0,
/// Port G pull-down bit y (y=0..10)
PD10: u1 = 0x0,
padding: u21 = 0,
}),
/// offset: 0x58
reserved88: [40]u8,
/// Power control register
/// offset: 0x80
PWR_CR5: mmio.Mmio(packed struct(u32) {
reserved8: u8 = 0,
/// Main regular range 1 mode
R1MODE: enum(u1) {
/// Main regulator in range 1 boost mode.
B_0x0 = 0x0,
/// Main regulator in range 1 normal mode.
B_0x1 = 0x1,
} = .B_0x1,
padding: u23 = 0,
}),
};

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src/stm32g4/types/peripherals/RCC.zig Normal file
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src/stm32g4/types/peripherals/RNG.zig Normal file
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const microzig = @import("microzig");
const mmio = microzig.mmio;
const types = @import("../../types.zig");
/// Random number generator
pub const RNG = extern struct {
/// control register
/// offset: 0x00
CR: mmio.Mmio(packed struct(u32) {
reserved2: u2 = 0,
/// Random number generator enable
RNGEN: u1 = 0x0,
/// Interrupt enable
IE: u1 = 0x0,
reserved5: u1 = 0,
/// Clock error detection
CED: u1 = 0x0,
padding: u26 = 0,
}),
/// status register
/// offset: 0x04
SR: mmio.Mmio(packed struct(u32) {
/// Data ready
DRDY: u1 = 0x0,
/// Clock error current status
CECS: u1 = 0x0,
/// Seed error current status
SECS: u1 = 0x0,
reserved5: u2 = 0,
/// Clock error interrupt status
CEIS: u1 = 0x0,
/// Seed error interrupt status
SEIS: u1 = 0x0,
padding: u25 = 0,
}),
/// data register
/// offset: 0x08
DR: mmio.Mmio(packed struct(u32) {
/// Random data
RNDATA: u32 = 0x0,
}),
};

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src/stm32g4/types/peripherals/RTC.zig Normal file
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const microzig = @import("microzig");
const mmio = microzig.mmio;
const types = @import("../../types.zig");
/// Real-time clock
pub const RTC = extern struct {
/// time register
/// offset: 0x00
TR: mmio.Mmio(packed struct(u32) {
/// Second units in BCD format
SU: u4 = 0x0,
/// Second tens in BCD format
ST: u3 = 0x0,
reserved8: u1 = 0,
/// Minute units in BCD format
MNU: u4 = 0x0,
/// Minute tens in BCD format
MNT: u3 = 0x0,
reserved16: u1 = 0,
/// Hour units in BCD format
HU: u4 = 0x0,
/// Hour tens in BCD format
HT: u2 = 0x0,
/// AM/PM notation
PM: u1 = 0x0,
padding: u9 = 0,
}),
/// date register
/// offset: 0x04
DR: mmio.Mmio(packed struct(u32) {
/// Date units in BCD format
DU: u4 = 0x1,
/// Date tens in BCD format
DT: u2 = 0x0,
reserved8: u2 = 0,
/// Month units in BCD format
MU: u4 = 0x1,
/// Month tens in BCD format
MT: u1 = 0x0,
/// Week day units
WDU: u3 = 0x1,
/// Year units in BCD format
YU: u4 = 0x0,
/// Year tens in BCD format
YT: u4 = 0x0,
padding: u8 = 0,
}),
/// sub second register
/// offset: 0x08
SSR: mmio.Mmio(packed struct(u32) {
/// Sub second value
SS: u16 = 0x0,
padding: u16 = 0,
}),
/// initialization and status register
/// offset: 0x0c
ICSR: mmio.Mmio(packed struct(u32) {
/// Alarm A write flag
ALRAWF: u1 = 0x1,
/// Alarm B write flag
ALRBWF: u1 = 0x1,
/// Wakeup timer write flag
WUTWF: u1 = 0x1,
/// Shift operation pending
SHPF: u1 = 0x0,
/// Initialization status flag
INITS: u1 = 0x0,
/// Registers synchronization flag
RSF: u1 = 0x0,
/// Initialization flag
INITF: u1 = 0x0,
/// Initialization mode
INIT: u1 = 0x0,
reserved16: u8 = 0,
/// Recalibration pending Flag
RECALPF: u1 = 0x0,
padding: u15 = 0,
}),
/// prescaler register
/// offset: 0x10
PRER: mmio.Mmio(packed struct(u32) {
/// Synchronous prescaler factor
PREDIV_S: u15 = 0xFF,
reserved16: u1 = 0,
/// Asynchronous prescaler factor
PREDIV_A: u7 = 0x7F,
padding: u9 = 0,
}),
/// wakeup timer register
/// offset: 0x14
WUTR: mmio.Mmio(packed struct(u32) {
/// Wakeup auto-reload value bits
WUT: u16 = 0xFFFF,
padding: u16 = 0,
}),
/// control register
/// offset: 0x18
CR: mmio.Mmio(packed struct(u32) {
/// Wakeup clock selection
WCKSEL: u3 = 0x0,
/// Time-stamp event active edge
TSEDGE: u1 = 0x0,
/// Reference clock detection enable (50 or 60 Hz)
REFCKON: u1 = 0x0,
/// Bypass the shadow registers
BYPSHAD: u1 = 0x0,
/// Hour format
FMT: u1 = 0x0,
reserved8: u1 = 0,
/// Alarm A enable
ALRAE: u1 = 0x0,
/// Alarm B enable
ALRBE: u1 = 0x0,
/// Wakeup timer enable
WUTE: u1 = 0x0,
/// Time stamp enable
TSE: u1 = 0x0,
/// Alarm A interrupt enable
ALRAIE: u1 = 0x0,
/// Alarm B interrupt enable
ALRBIE: u1 = 0x0,
/// Wakeup timer interrupt enable
WUTIE: u1 = 0x0,
/// Time-stamp interrupt enable
TSIE: u1 = 0x0,
/// Add 1 hour (summer time change)
ADD1H: u1 = 0x0,
/// Subtract 1 hour (winter time change)
SUB1H: u1 = 0x0,
/// Backup
BKP: u1 = 0x0,
/// Calibration output selection
COSEL: u1 = 0x0,
/// Output polarity
POL: u1 = 0x0,
/// Output selection
OSEL: u2 = 0x0,
/// Calibration output enable
COE: u1 = 0x0,
/// timestamp on internal event enable
ITSE: u1 = 0x0,
/// TAMPTS
TAMPTS: u1 = 0x0,
/// TAMPOE
TAMPOE: u1 = 0x0,
reserved29: u2 = 0,
/// TAMPALRM_PU
TAMPALRM_PU: u1 = 0x0,
/// TAMPALRM_TYPE
TAMPALRM_TYPE: u1 = 0x0,
/// OUT2EN
OUT2EN: u1 = 0x0,
}),
/// offset: 0x1c
reserved28: [8]u8,
/// write protection register
/// offset: 0x24
WPR: mmio.Mmio(packed struct(u32) {
/// Write protection key
KEY: u8 = 0x0,
padding: u24 = 0,
}),
/// calibration register
/// offset: 0x28
CALR: mmio.Mmio(packed struct(u32) {
/// Calibration minus
CALM: u9 = 0x0,
reserved13: u4 = 0,
/// Use a 16-second calibration cycle period
CALW16: u1 = 0x0,
/// Use an 8-second calibration cycle period
CALW8: u1 = 0x0,
/// Increase frequency of RTC by 488.5 ppm
CALP: u1 = 0x0,
padding: u16 = 0,
}),
/// shift control register
/// offset: 0x2c
SHIFTR: mmio.Mmio(packed struct(u32) {
/// Subtract a fraction of a second
SUBFS: u15 = 0x0,
reserved31: u16 = 0,
/// Add one second
ADD1S: u1 = 0x0,
}),
/// time stamp time register
/// offset: 0x30
TSTR: mmio.Mmio(packed struct(u32) {
/// Second units in BCD format
SU: u4 = 0x0,
/// Second tens in BCD format
ST: u3 = 0x0,
reserved8: u1 = 0,
/// Minute units in BCD format
MNU: u4 = 0x0,
/// Minute tens in BCD format
MNT: u3 = 0x0,
reserved16: u1 = 0,
/// Hour units in BCD format
HU: u4 = 0x0,
/// Hour tens in BCD format
HT: u2 = 0x0,
/// AM/PM notation
PM: u1 = 0x0,
padding: u9 = 0,
}),
/// time stamp date register
/// offset: 0x34
TSDR: mmio.Mmio(packed struct(u32) {
/// Date units in BCD format
DU: u4 = 0x0,
/// Date tens in BCD format
DT: u2 = 0x0,
reserved8: u2 = 0,
/// Month units in BCD format
MU: u4 = 0x0,
/// Month tens in BCD format
MT: u1 = 0x0,
/// Week day units
WDU: u3 = 0x0,
padding: u16 = 0,
}),
/// timestamp sub second register
/// offset: 0x38
TSSSR: mmio.Mmio(packed struct(u32) {
/// Sub second value
SS: u16 = 0x0,
padding: u16 = 0,
}),
/// offset: 0x3c
reserved60: [4]u8,
/// alarm A register
/// offset: 0x40
ALRMAR: mmio.Mmio(packed struct(u32) {
/// Second units in BCD format
SU: u4 = 0x0,
/// Second tens in BCD format
ST: u3 = 0x0,
/// Alarm A seconds mask
MSK1: u1 = 0x0,
/// Minute units in BCD format
MNU: u4 = 0x0,
/// Minute tens in BCD format
MNT: u3 = 0x0,
/// Alarm A minutes mask
MSK2: u1 = 0x0,
/// Hour units in BCD format
HU: u4 = 0x0,
/// Hour tens in BCD format
HT: u2 = 0x0,
/// AM/PM notation
PM: u1 = 0x0,
/// Alarm A hours mask
MSK3: u1 = 0x0,
/// Date units or day in BCD format
DU: u4 = 0x0,
/// Date tens in BCD format
DT: u2 = 0x0,
/// Week day selection
WDSEL: u1 = 0x0,
/// Alarm A date mask
MSK4: u1 = 0x0,
}),
/// alarm A sub second register
/// offset: 0x44
ALRMASSR: mmio.Mmio(packed struct(u32) {
/// Sub seconds value
SS: u15 = 0x0,
reserved24: u9 = 0,
/// Mask the most-significant bits starting at this bit
MASKSS: u4 = 0x0,
padding: u4 = 0,
}),
/// alarm B register
/// offset: 0x48
ALRMBR: mmio.Mmio(packed struct(u32) {
/// Second units in BCD format
SU: u4 = 0x0,
/// Second tens in BCD format
ST: u3 = 0x0,
/// Alarm B seconds mask
MSK1: u1 = 0x0,
/// Minute units in BCD format
MNU: u4 = 0x0,
/// Minute tens in BCD format
MNT: u3 = 0x0,
/// Alarm B minutes mask
MSK2: u1 = 0x0,
/// Hour units in BCD format
HU: u4 = 0x0,
/// Hour tens in BCD format
HT: u2 = 0x0,
/// AM/PM notation
PM: u1 = 0x0,
/// Alarm B hours mask
MSK3: u1 = 0x0,
/// Date units or day in BCD format
DU: u4 = 0x0,
/// Date tens in BCD format
DT: u2 = 0x0,
/// Week day selection
WDSEL: u1 = 0x0,
/// Alarm B date mask
MSK4: u1 = 0x0,
}),
/// alarm B sub second register
/// offset: 0x4c
ALRMBSSR: mmio.Mmio(packed struct(u32) {
/// Sub seconds value
SS: u15 = 0x0,
reserved24: u9 = 0,
/// Mask the most-significant bits starting at this bit
MASKSS: u4 = 0x0,
padding: u4 = 0,
}),
/// status register
/// offset: 0x50
SR: mmio.Mmio(packed struct(u32) {
/// ALRAF
ALRAF: u1 = 0x0,
/// ALRBF
ALRBF: u1 = 0x0,
/// WUTF
WUTF: u1 = 0x0,
/// TSF
TSF: u1 = 0x0,
/// TSOVF
TSOVF: u1 = 0x0,
/// ITSF
ITSF: u1 = 0x0,
padding: u26 = 0,
}),
/// status register
/// offset: 0x54
MISR: mmio.Mmio(packed struct(u32) {
/// ALRAMF
ALRAMF: u1 = 0x0,
/// ALRBMF
ALRBMF: u1 = 0x0,
/// WUTMF
WUTMF: u1 = 0x0,
/// TSMF
TSMF: u1 = 0x0,
/// TSOVMF
TSOVMF: u1 = 0x0,
/// ITSMF
ITSMF: u1 = 0x0,
padding: u26 = 0,
}),
/// offset: 0x58
reserved88: [4]u8,
/// status register
/// offset: 0x5c
SCR: mmio.Mmio(packed struct(u32) {
/// CALRAF
CALRAF: u1 = 0x0,
/// CALRBF
CALRBF: u1 = 0x0,
/// CWUTF
CWUTF: u1 = 0x0,
/// CTSF
CTSF: u1 = 0x0,
/// CTSOVF
CTSOVF: u1 = 0x0,
/// CITSF
CITSF: u1 = 0x0,
padding: u26 = 0,
}),
};

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src/stm32g4/types/peripherals/SAI.zig Normal file
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const microzig = @import("microzig");
const mmio = microzig.mmio;
const types = @import("../../types.zig");
/// Serial audio interface
pub const SAI = extern struct {
/// offset: 0x00
reserved0: [4]u8,
/// AConfiguration register 1
/// offset: 0x04
ACR1: mmio.Mmio(packed struct(u32) {
/// Audio block mode
MODE: u2 = 0x0,
/// Protocol configuration
PRTCFG: u2 = 0x0,
reserved5: u1 = 0,
/// Data size
DS: u3 = 0x2,
/// Least significant bit first
LSBFIRST: u1 = 0x0,
/// Clock strobing edge
CKSTR: u1 = 0x0,
/// Synchronization enable
SYNCEN: u2 = 0x0,
/// Mono mode
MONO: u1 = 0x0,
/// Output drive
OutDri: u1 = 0x0,
reserved16: u2 = 0,
/// Audio block A enable
SAIAEN: u1 = 0x0,
/// DMA enable
DMAEN: u1 = 0x0,
reserved19: u1 = 0,
/// No divider
NODIV: u1 = 0x0,
/// Master clock divider
MCJDIV: u6 = 0x0,
/// OSR
OSR: u1 = 0x0,
/// MCKEN
MCKEN: u1 = 0x0,
padding: u4 = 0,
}),
/// AConfiguration register 2
/// offset: 0x08
ACR2: mmio.Mmio(packed struct(u32) {
/// FIFO threshold
FTH: u3 = 0x0,
/// FIFO flush
FFLUS: u1 = 0x0,
/// Tristate management on data line
TRIS: u1 = 0x0,
/// Mute
MUTE: u1 = 0x0,
/// Mute value
MUTEVAL: u1 = 0x0,
/// Mute counter
MUTECN: u6 = 0x0,
/// Complement bit
CPL: u1 = 0x0,
/// Companding mode
COMP: u2 = 0x0,
padding: u16 = 0,
}),
/// AFRCR
/// offset: 0x0c
AFRCR: mmio.Mmio(packed struct(u32) {
/// Frame length
FRL: u8 = 0x7,
/// Frame synchronization active level length
FSALL: u7 = 0x0,
reserved16: u1 = 0,
/// Frame synchronization definition
FSDEF: u1 = 0x0,
/// Frame synchronization polarity
FSPOL: u1 = 0x0,
/// Frame synchronization offset
FSOFF: u1 = 0x0,
padding: u13 = 0,
}),
/// ASlot register
/// offset: 0x10
ASLOTR: mmio.Mmio(packed struct(u32) {
/// First bit offset
FBOFF: u5 = 0x0,
reserved6: u1 = 0,
/// Slot size
SLOTSZ: u2 = 0x0,
/// Number of slots in an audio frame
NBSLOT: u4 = 0x0,
reserved16: u4 = 0,
/// Slot enable
SLOTEN: u16 = 0x0,
}),
/// AInterrupt mask register2
/// offset: 0x14
AIM: mmio.Mmio(packed struct(u32) {
/// Overrun/underrun interrupt enable
OVRUDRIE: u1 = 0x0,
/// Mute detection interrupt enable
MUTEDET: u1 = 0x0,
/// Wrong clock configuration interrupt enable
WCKCFG: u1 = 0x0,
/// FIFO request interrupt enable
FREQIE: u1 = 0x0,
/// Codec not ready interrupt enable
CNRDYIE: u1 = 0x0,
/// Anticipated frame synchronization detection interrupt enable
AFSDETIE: u1 = 0x0,
/// Late frame synchronization detection interrupt enable
LFSDET: u1 = 0x0,
padding: u25 = 0,
}),
/// AStatus register
/// offset: 0x18
ASR: mmio.Mmio(packed struct(u32) {
/// Overrun / underrun
OVRUDR: u1 = 0x0,
/// Mute detection
MUTEDET: u1 = 0x0,
/// Wrong clock configuration flag. This bit is read only
WCKCFG: u1 = 0x0,
/// FIFO request
FREQ: u1 = 0x0,
/// Codec not ready
CNRDY: u1 = 0x0,
/// Anticipated frame synchronization detection
AFSDET: u1 = 0x0,
/// Late frame synchronization detection
LFSDET: u1 = 0x0,
reserved16: u9 = 0,
/// FIFO level threshold
FLVL: u3 = 0x0,
padding: u13 = 0,
}),
/// AClear flag register
/// offset: 0x1c
ACLRFR: mmio.Mmio(packed struct(u32) {
/// Clear overrun / underrun
OVRUDR: u1 = 0x0,
/// Mute detection flag
MUTEDET: u1 = 0x0,
/// Clear wrong clock configuration flag
WCKCFG: u1 = 0x0,
reserved4: u1 = 0,
/// Clear codec not ready flag
CNRDY: u1 = 0x0,
/// Clear anticipated frame synchronization detection flag
CAFSDET: u1 = 0x0,
/// Clear late frame synchronization detection flag
LFSDET: u1 = 0x0,
padding: u25 = 0,
}),
/// AData register
/// offset: 0x20
ADR: mmio.Mmio(packed struct(u32) {
/// Data
DATA: u32 = 0x0,
}),
/// BConfiguration register 1
/// offset: 0x24
BCR1: mmio.Mmio(packed struct(u32) {
/// Audio block mode
MODE: u2 = 0x0,
/// Protocol configuration
PRTCFG: u2 = 0x0,
reserved5: u1 = 0,
/// Data size
DS: u3 = 0x2,
/// Least significant bit first
LSBFIRST: u1 = 0x0,
/// Clock strobing edge
CKSTR: u1 = 0x0,
/// Synchronization enable
SYNCEN: u2 = 0x0,
/// Mono mode
MONO: u1 = 0x0,
/// Output drive
OutDri: u1 = 0x0,
reserved16: u2 = 0,
/// Audio block B enable
SAIBEN: u1 = 0x0,
/// DMA enable
DMAEN: u1 = 0x0,
reserved19: u1 = 0,
/// No divider
NODIV: u1 = 0x0,
/// Master clock divider
MCJDIV: u6 = 0x0,
/// OSR
OSR: u1 = 0x0,
/// MCKEN
MCKEN: u1 = 0x0,
padding: u4 = 0,
}),
/// BConfiguration register 2
/// offset: 0x28
BCR2: mmio.Mmio(packed struct(u32) {
/// FIFO threshold
FTH: u3 = 0x0,
/// FIFO flush
FFLUS: u1 = 0x0,
/// Tristate management on data line
TRIS: u1 = 0x0,
/// Mute
MUTE: u1 = 0x0,
/// Mute value
MUTEVAL: u1 = 0x0,
/// Mute counter
MUTECN: u6 = 0x0,
/// Complement bit
CPL: u1 = 0x0,
/// Companding mode
COMP: u2 = 0x0,
padding: u16 = 0,
}),
/// BFRCR
/// offset: 0x2c
BFRCR: mmio.Mmio(packed struct(u32) {
/// Frame length
FRL: u8 = 0x7,
/// Frame synchronization active level length
FSALL: u7 = 0x0,
reserved16: u1 = 0,
/// Frame synchronization definition
FSDEF: u1 = 0x0,
/// Frame synchronization polarity
FSPOL: u1 = 0x0,
/// Frame synchronization offset
FSOFF: u1 = 0x0,
padding: u13 = 0,
}),
/// BSlot register
/// offset: 0x30
BSLOTR: mmio.Mmio(packed struct(u32) {
/// First bit offset
FBOFF: u5 = 0x0,
reserved6: u1 = 0,
/// Slot size
SLOTSZ: u2 = 0x0,
/// Number of slots in an audio frame
NBSLOT: u4 = 0x0,
reserved16: u4 = 0,
/// Slot enable
SLOTEN: u16 = 0x0,
}),
/// BInterrupt mask register2
/// offset: 0x34
BIM: mmio.Mmio(packed struct(u32) {
/// Overrun/underrun interrupt enable
OVRUDRIE: u1 = 0x0,
/// Mute detection interrupt enable
MUTEDET: u1 = 0x0,
/// Wrong clock configuration interrupt enable
WCKCFG: u1 = 0x0,
/// FIFO request interrupt enable
FREQIE: u1 = 0x0,
/// Codec not ready interrupt enable
CNRDYIE: u1 = 0x0,
/// Anticipated frame synchronization detection interrupt enable
AFSDETIE: u1 = 0x0,
/// Late frame synchronization detection interrupt enable
LFSDETIE: u1 = 0x0,
padding: u25 = 0,
}),
/// BStatus register
/// offset: 0x38
BSR: mmio.Mmio(packed struct(u32) {
/// Overrun / underrun
OVRUDR: u1 = 0x0,
/// Mute detection
MUTEDET: u1 = 0x0,
/// Wrong clock configuration flag
WCKCFG: u1 = 0x0,
/// FIFO request
FREQ: u1 = 0x0,
/// Codec not ready
CNRDY: u1 = 0x0,
/// Anticipated frame synchronization detection
AFSDET: u1 = 0x0,
/// Late frame synchronization detection
LFSDET: u1 = 0x0,
reserved16: u9 = 0,
/// FIFO level threshold
FLVL: u3 = 0x0,
padding: u13 = 0,
}),
/// BClear flag register
/// offset: 0x3c
BCLRFR: mmio.Mmio(packed struct(u32) {
/// Clear overrun / underrun
OVRUDR: u1 = 0x0,
/// Mute detection flag
MUTEDET: u1 = 0x0,
/// Clear wrong clock configuration flag
WCKCFG: u1 = 0x0,
reserved4: u1 = 0,
/// Clear codec not ready flag
CNRDY: u1 = 0x0,
/// Clear anticipated frame synchronization detection flag
CAFSDET: u1 = 0x0,
/// Clear late frame synchronization detection flag
LFSDET: u1 = 0x0,
padding: u25 = 0,
}),
/// BData register
/// offset: 0x40
BDR: mmio.Mmio(packed struct(u32) {
/// Data
DATA: u32 = 0x0,
}),
/// PDM control register
/// offset: 0x44
PDMCR: mmio.Mmio(packed struct(u32) {
/// PDMEN
PDMEN: u1 = 0x0,
reserved4: u3 = 0,
/// MICNBR
MICNBR: u2 = 0x0,
reserved8: u2 = 0,
/// CKEN1
CKEN1: u1 = 0x0,
/// CKEN2
CKEN2: u1 = 0x0,
/// CKEN3
CKEN3: u1 = 0x0,
/// CKEN4
CKEN4: u1 = 0x0,
padding: u20 = 0,
}),
/// PDM delay register
/// offset: 0x48
PDMDLY: mmio.Mmio(packed struct(u32) {
/// DLYM1L
DLYM1L: u3 = 0x0,
reserved4: u1 = 0,
/// DLYM1R
DLYM1R: u3 = 0x0,
reserved8: u1 = 0,
/// DLYM2L
DLYM2L: u3 = 0x0,
reserved12: u1 = 0,
/// DLYM2R
DLYM2R: u3 = 0x0,
reserved16: u1 = 0,
/// DLYM3L
DLYM3L: u3 = 0x0,
reserved20: u1 = 0,
/// DLYM3R
DLYM3R: u3 = 0x0,
reserved24: u1 = 0,
/// DLYM4L
DLYM4L: u3 = 0x0,
reserved28: u1 = 0,
/// DLYM4R
DLYM4R: u3 = 0x0,
padding: u1 = 0,
}),
};

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src/stm32g4/types/peripherals/SPI1.zig Normal file
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const microzig = @import("microzig");
const mmio = microzig.mmio;
const types = @import("../../types.zig");
/// Serial peripheral interface/Inter-IC sound
pub const SPI1 = extern struct {
/// control register 1
/// offset: 0x00
CR1: mmio.Mmio(packed struct(u32) {
/// Clock phase
CPHA: u1 = 0x0,
/// Clock polarity
CPOL: u1 = 0x0,
/// Master selection
MSTR: u1 = 0x0,
/// Baud rate control
BR: u3 = 0x0,
/// SPI enable
SPE: u1 = 0x0,
/// Frame format
LSBFIRST: u1 = 0x0,
/// Internal slave select
SSI: u1 = 0x0,
/// Software slave management
SSM: u1 = 0x0,
/// Receive only
RXONLY: u1 = 0x0,
/// Data frame format
DFF: u1 = 0x0,
/// CRC transfer next
CRCNEXT: u1 = 0x0,
/// Hardware CRC calculation enable
CRCEN: u1 = 0x0,
/// Output enable in bidirectional mode
BIDIOE: u1 = 0x0,
/// Bidirectional data mode enable
BIDIMODE: u1 = 0x0,
padding: u16 = 0,
}),
/// control register 2
/// offset: 0x04
CR2: mmio.Mmio(packed struct(u32) {
/// Rx buffer DMA enable
RXDMAEN: u1 = 0x0,
/// Tx buffer DMA enable
TXDMAEN: u1 = 0x0,
/// SS output enable
SSOE: u1 = 0x0,
/// NSS pulse management
NSSP: u1 = 0x0,
/// Frame format
FRF: u1 = 0x0,
/// Error interrupt enable
ERRIE: u1 = 0x0,
/// RX buffer not empty interrupt enable
RXNEIE: u1 = 0x0,
/// Tx buffer empty interrupt enable
TXEIE: u1 = 0x0,
/// Data size
DS: u4 = 0x7,
/// FIFO reception threshold
FRXTH: u1 = 0x0,
/// Last DMA transfer for reception
LDMA_RX: u1 = 0x0,
/// Last DMA transfer for transmission
LDMA_TX: u1 = 0x0,
padding: u17 = 0,
}),
/// status register
/// offset: 0x08
SR: mmio.Mmio(packed struct(u32) {
/// Receive buffer not empty
RXNE: u1 = 0x0,
/// Transmit buffer empty
TXE: u1 = 0x1,
reserved4: u2 = 0,
/// CRC error flag
CRCERR: u1 = 0x0,
/// Mode fault
MODF: u1 = 0x0,
/// Overrun flag
OVR: u1 = 0x0,
/// Busy flag
BSY: u1 = 0x0,
/// TI frame format error
TIFRFE: u1 = 0x0,
/// FIFO reception level
FRLVL: u2 = 0x0,
/// FIFO transmission level
FTLVL: u2 = 0x0,
padding: u19 = 0,
}),
/// data register
/// offset: 0x0c
DR: mmio.Mmio(packed struct(u32) {
/// Data register
DR: u16 = 0x0,
padding: u16 = 0,
}),
/// CRC polynomial register
/// offset: 0x10
CRCPR: mmio.Mmio(packed struct(u32) {
/// CRC polynomial register
CRCPOLY: u16 = 0x7,
padding: u16 = 0,
}),
/// RX CRC register
/// offset: 0x14
RXCRCR: mmio.Mmio(packed struct(u32) {
/// Rx CRC register
RxCRC: u16 = 0x0,
padding: u16 = 0,
}),
/// TX CRC register
/// offset: 0x18
TXCRCR: mmio.Mmio(packed struct(u32) {
/// Tx CRC register
TxCRC: u16 = 0x0,
padding: u16 = 0,
}),
/// configuration register
/// offset: 0x1c
I2SCFGR: mmio.Mmio(packed struct(u32) {
/// CHLEN
CHLEN: u1 = 0x0,
/// DATLEN
DATLEN: u2 = 0x0,
/// CKPOL
CKPOL: u1 = 0x0,
/// I2SSTD
I2SSTD: u2 = 0x0,
reserved7: u1 = 0,
/// PCMSYNC
PCMSYNC: u1 = 0x0,
/// I2SCFG
I2SCFG: u2 = 0x0,
/// I2SE
I2SE: u1 = 0x0,
/// I2SMOD
I2SMOD: u1 = 0x0,
padding: u20 = 0,
}),
/// prescaler register
/// offset: 0x20
I2SPR: mmio.Mmio(packed struct(u32) {
/// I2SDIV
I2SDIV: u8 = 0x2,
/// ODD
ODD: u1 = 0x0,
/// MCKOE
MCKOE: u1 = 0x0,
padding: u22 = 0,
}),
};

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src/stm32g4/types/peripherals/SYSCFG.zig Normal file
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const microzig = @import("microzig");
const mmio = microzig.mmio;
const types = @import("../../types.zig");
/// System configuration controller
pub const SYSCFG = extern struct {
/// Remap Memory register
/// offset: 0x00
MEMRMP: mmio.Mmio(packed struct(u32) {
/// Memory mapping selection
MEM_MODE: u3 = 0x0,
reserved8: u5 = 0,
/// User Flash Bank mode
FB_mode: u1 = 0x0,
padding: u23 = 0,
}),
/// peripheral mode configuration register
/// offset: 0x04
CFGR1: mmio.Mmio(packed struct(u32) {
reserved8: u8 = 0,
/// BOOSTEN
BOOSTEN: u1 = 0x0,
/// GPIO analog switch control voltage selection
ANASWVDD: u1 = 0x0,
reserved16: u6 = 0,
/// FM+ drive capability on PB6
I2C_PB6_FMP: u1 = 0x0,
/// FM+ drive capability on PB6
I2C_PB7_FMP: u1 = 0x0,
/// FM+ drive capability on PB6
I2C_PB8_FMP: u1 = 0x0,
/// FM+ drive capability on PB6
I2C_PB9_FMP: u1 = 0x0,
/// I2C1 FM+ drive capability enable
I2C1_FMP: u1 = 0x0,
/// I2C1 FM+ drive capability enable
I2C2_FMP: u1 = 0x0,
/// I2C1 FM+ drive capability enable
I2C3_FMP: u1 = 0x0,
/// I2C1 FM+ drive capability enable
I2C4_FMP: u1 = 0x0,
reserved26: u2 = 0,
/// FPU Interrupts Enable
FPU_IE: u6 = 0x1F,
}),
/// external interrupt configuration register 1
/// offset: 0x08
EXTICR1: mmio.Mmio(packed struct(u32) {
/// EXTI x configuration (x = 0 to 3)
EXTI0: u4 = 0x0,
/// EXTI x configuration (x = 0 to 3)
EXTI1: u4 = 0x0,
/// EXTI x configuration (x = 0 to 3)
EXTI2: u4 = 0x0,
/// EXTI x configuration (x = 0 to 3)
EXTI3: u4 = 0x0,
padding: u16 = 0,
}),
/// external interrupt configuration register 2
/// offset: 0x0c
EXTICR2: mmio.Mmio(packed struct(u32) {
/// EXTI x configuration (x = 4 to 7)
EXTI4: u4 = 0x0,
/// EXTI x configuration (x = 4 to 7)
EXTI5: u4 = 0x0,
/// EXTI x configuration (x = 4 to 7)
EXTI6: u4 = 0x0,
/// EXTI x configuration (x = 4 to 7)
EXTI7: u4 = 0x0,
padding: u16 = 0,
}),
/// external interrupt configuration register 3
/// offset: 0x10
EXTICR3: mmio.Mmio(packed struct(u32) {
/// EXTI x configuration (x = 8 to 11)
EXTI8: u4 = 0x0,
/// EXTI x configuration (x = 8 to 11)
EXTI9: u4 = 0x0,
/// EXTI10
EXTI10: u4 = 0x0,
/// EXTI x configuration (x = 8 to 11)
EXTI11: u4 = 0x0,
padding: u16 = 0,
}),
/// external interrupt configuration register 4
/// offset: 0x14
EXTICR4: mmio.Mmio(packed struct(u32) {
/// EXTI x configuration (x = 12 to 15)
EXTI12: u4 = 0x0,
/// EXTI x configuration (x = 12 to 15)
EXTI13: u4 = 0x0,
/// EXTI x configuration (x = 12 to 15)
EXTI14: u4 = 0x0,
/// EXTI x configuration (x = 12 to 15)
EXTI15: u4 = 0x0,
padding: u16 = 0,
}),
/// CCM SRAM control and status register
/// offset: 0x18
SCSR: mmio.Mmio(packed struct(u32) {
/// CCM SRAM Erase
CCMER: u1 = 0x0,
/// CCM SRAM busy by erase operation
CCMBSY: u1 = 0x0,
padding: u30 = 0,
}),
/// configuration register 2
/// offset: 0x1c
CFGR2: mmio.Mmio(packed struct(u32) {
/// Core Lockup Lock
CLL: u1 = 0x0,
/// SRAM Parity Lock
SPL: u1 = 0x0,
/// PVD Lock
PVDL: u1 = 0x0,
/// ECC Lock
ECCL: u1 = 0x0,
reserved8: u4 = 0,
/// SRAM Parity Flag
SPF: u1 = 0x0,
padding: u23 = 0,
}),
/// SRAM Write protection register 1
/// offset: 0x20
SWPR: mmio.Mmio(packed struct(u32) {
/// Write protection
Page0_WP: u1 = 0x0,
/// Write protection
Page1_WP: u1 = 0x0,
/// Write protection
Page2_WP: u1 = 0x0,
/// Write protection
Page3_WP: u1 = 0x0,
/// Write protection
Page4_WP: u1 = 0x0,
/// Write protection
Page5_WP: u1 = 0x0,
/// Write protection
Page6_WP: u1 = 0x0,
/// Write protection
Page7_WP: u1 = 0x0,
/// Write protection
Page8_WP: u1 = 0x0,
/// Write protection
Page9_WP: u1 = 0x0,
/// Write protection
Page10_WP: u1 = 0x0,
/// Write protection
Page11_WP: u1 = 0x0,
/// Write protection
Page12_WP: u1 = 0x0,
/// Write protection
Page13_WP: u1 = 0x0,
/// Write protection
Page14_WP: u1 = 0x0,
/// Write protection
Page15_WP: u1 = 0x0,
/// Write protection
Page16_WP: u1 = 0x0,
/// Write protection
Page17_WP: u1 = 0x0,
/// Write protection
Page18_WP: u1 = 0x0,
/// Write protection
Page19_WP: u1 = 0x0,
/// Write protection
Page20_WP: u1 = 0x0,
/// Write protection
Page21_WP: u1 = 0x0,
/// Write protection
Page22_WP: u1 = 0x0,
/// Write protection
Page23_WP: u1 = 0x0,
/// Write protection
Page24_WP: u1 = 0x0,
/// Write protection
Page25_WP: u1 = 0x0,
/// Write protection
Page26_WP: u1 = 0x0,
/// Write protection
Page27_WP: u1 = 0x0,
/// Write protection
Page28_WP: u1 = 0x0,
/// Write protection
Page29_WP: u1 = 0x0,
/// Write protection
Page30_WP: u1 = 0x0,
/// Write protection
Page31_WP: u1 = 0x0,
}),
/// SRAM2 Key Register
/// offset: 0x24
SKR: mmio.Mmio(packed struct(u32) {
/// SRAM2 Key for software erase
KEY: u8 = 0x0,
padding: u24 = 0,
}),
};

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src/stm32g4/types/peripherals/TAMP.zig Normal file
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const microzig = @import("microzig");
const mmio = microzig.mmio;
const types = @import("../../types.zig");
/// Tamper and backup registers
pub const TAMP = extern struct {
/// control register 1
/// offset: 0x00
CR1: mmio.Mmio(packed struct(u32) {
/// TAMP1E
TAMP1E: u1 = 0x0,
/// TAMP2E
TAMP2E: u1 = 0x0,
/// TAMP2E
TAMP3E: u1 = 0x0,
reserved18: u15 = 0,
/// ITAMP3E
ITAMP3E: u1 = 0x1,
/// ITAMP4E
ITAMP4E: u1 = 0x1,
/// ITAMP5E
ITAMP5E: u1 = 0x1,
/// ITAMP6E
ITAMP6E: u1 = 0x1,
padding: u10 = 0,
}),
/// control register 2
/// offset: 0x04
CR2: mmio.Mmio(packed struct(u32) {
/// TAMP1NOER
TAMP1NOER: u1 = 0x0,
/// TAMP2NOER
TAMP2NOER: u1 = 0x0,
/// TAMP3NOER
TAMP3NOER: u1 = 0x0,
reserved16: u13 = 0,
/// TAMP1MSK
TAMP1MSK: u1 = 0x0,
/// TAMP2MSK
TAMP2MSK: u1 = 0x0,
/// TAMP3MSK
TAMP3MSK: u1 = 0x0,
reserved24: u5 = 0,
/// TAMP1TRG
TAMP1TRG: u1 = 0x0,
/// TAMP2TRG
TAMP2TRG: u1 = 0x0,
/// TAMP3TRG
TAMP3TRG: u1 = 0x0,
padding: u5 = 0,
}),
/// offset: 0x08
reserved8: [4]u8,
/// TAMP filter control register
/// offset: 0x0c
FLTCR: mmio.Mmio(packed struct(u32) {
/// TAMPFREQ
TAMPFREQ: u3 = 0x0,
/// TAMPFLT
TAMPFLT: u2 = 0x0,
/// TAMPPRCH
TAMPPRCH: u2 = 0x0,
/// TAMPPUDIS
TAMPPUDIS: u1 = 0x0,
padding: u24 = 0,
}),
/// offset: 0x10
reserved16: [28]u8,
/// TAMP interrupt enable register
/// offset: 0x2c
IER: mmio.Mmio(packed struct(u32) {
/// TAMP1IE
TAMP1IE: u1 = 0x0,
/// TAMP2IE
TAMP2IE: u1 = 0x0,
/// TAMP3IE
TAMP3IE: u1 = 0x0,
reserved18: u15 = 0,
/// ITAMP3IE
ITAMP3IE: u1 = 0x0,
/// ITAMP4IE
ITAMP4IE: u1 = 0x0,
/// ITAMP5IE
ITAMP5IE: u1 = 0x0,
/// ITAMP6IE
ITAMP6IE: u1 = 0x0,
padding: u10 = 0,
}),
/// TAMP status register
/// offset: 0x30
SR: mmio.Mmio(packed struct(u32) {
/// TAMP1F
TAMP1F: u1 = 0x0,
/// TAMP2F
TAMP2F: u1 = 0x0,
/// TAMP3F
TAMP3F: u1 = 0x0,
reserved18: u15 = 0,
/// ITAMP3F
ITAMP3F: u1 = 0x0,
/// ITAMP4F
ITAMP4F: u1 = 0x0,
/// ITAMP5F
ITAMP5F: u1 = 0x0,
/// ITAMP6F
ITAMP6F: u1 = 0x0,
padding: u10 = 0,
}),
/// TAMP masked interrupt status register
/// offset: 0x34
MISR: mmio.Mmio(packed struct(u32) {
/// TAMP1MF:
TAMP1MF: u1 = 0x0,
/// TAMP2MF
TAMP2MF: u1 = 0x0,
/// TAMP3MF
TAMP3MF: u1 = 0x0,
reserved18: u15 = 0,
/// ITAMP3MF
ITAMP3MF: u1 = 0x0,
/// ITAMP4MF
ITAMP4MF: u1 = 0x0,
/// ITAMP5MF
ITAMP5MF: u1 = 0x0,
/// ITAMP6MF
ITAMP6MF: u1 = 0x0,
padding: u10 = 0,
}),
/// offset: 0x38
reserved56: [4]u8,
/// TAMP status clear register
/// offset: 0x3c
SCR: mmio.Mmio(packed struct(u32) {
/// CTAMP1F
CTAMP1F: u1 = 0x0,
/// CTAMP2F
CTAMP2F: u1 = 0x0,
/// CTAMP3F
CTAMP3F: u1 = 0x0,
reserved18: u15 = 0,
/// CITAMP3F
CITAMP3F: u1 = 0x0,
/// CITAMP4F
CITAMP4F: u1 = 0x0,
/// CITAMP5F
CITAMP5F: u1 = 0x0,
/// CITAMP6F
CITAMP6F: u1 = 0x0,
padding: u10 = 0,
}),
/// offset: 0x40
reserved64: [192]u8,
/// TAMP backup register
/// offset: 0x100
BKP0R: mmio.Mmio(packed struct(u32) {
/// BKP
BKP: u32 = 0x0,
}),
/// TAMP backup register
/// offset: 0x104
BKP1R: mmio.Mmio(packed struct(u32) {
/// BKP
BKP: u32 = 0x0,
}),
/// TAMP backup register
/// offset: 0x108
BKP2R: mmio.Mmio(packed struct(u32) {
/// BKP
BKP: u32 = 0x0,
}),
/// TAMP backup register
/// offset: 0x10c
BKP3R: mmio.Mmio(packed struct(u32) {
/// BKP
BKP: u32 = 0x0,
}),
/// TAMP backup register
/// offset: 0x110
BKP4R: mmio.Mmio(packed struct(u32) {
/// BKP
BKP: u32 = 0x0,
}),
/// TAMP backup register
/// offset: 0x114
BKP5R: mmio.Mmio(packed struct(u32) {
/// BKP
BKP: u32 = 0x0,
}),
/// TAMP backup register
/// offset: 0x118
BKP6R: mmio.Mmio(packed struct(u32) {
/// BKP
BKP: u32 = 0x0,
}),
/// TAMP backup register
/// offset: 0x11c
BKP7R: mmio.Mmio(packed struct(u32) {
/// BKP
BKP: u32 = 0x0,
}),
/// TAMP backup register
/// offset: 0x120
BKP8R: mmio.Mmio(packed struct(u32) {
/// BKP
BKP: u32 = 0x0,
}),
/// TAMP backup register
/// offset: 0x124
BKP9R: mmio.Mmio(packed struct(u32) {
/// BKP
BKP: u32 = 0x0,
}),
/// TAMP backup register
/// offset: 0x128
BKP10R: mmio.Mmio(packed struct(u32) {
/// BKP
BKP: u32 = 0x0,
}),
/// TAMP backup register
/// offset: 0x12c
BKP11R: mmio.Mmio(packed struct(u32) {
/// BKP
BKP: u32 = 0x0,
}),
/// TAMP backup register
/// offset: 0x130
BKP12R: mmio.Mmio(packed struct(u32) {
/// BKP
BKP: u32 = 0x0,
}),
/// TAMP backup register
/// offset: 0x134
BKP13R: mmio.Mmio(packed struct(u32) {
/// BKP
BKP: u32 = 0x0,
}),
/// TAMP backup register
/// offset: 0x138
BKP14R: mmio.Mmio(packed struct(u32) {
/// BKP
BKP: u32 = 0x0,
}),
/// TAMP backup register
/// offset: 0x13c
BKP15R: mmio.Mmio(packed struct(u32) {
/// BKP
BKP: u32 = 0x0,
}),
/// TAMP backup register
/// offset: 0x140
BKP16R: mmio.Mmio(packed struct(u32) {
/// BKP
BKP: u32 = 0x0,
}),
/// TAMP backup register
/// offset: 0x144
BKP17R: mmio.Mmio(packed struct(u32) {
/// BKP
BKP: u32 = 0x0,
}),
/// TAMP backup register
/// offset: 0x148
BKP18R: mmio.Mmio(packed struct(u32) {
/// BKP
BKP: u32 = 0x0,
}),
/// TAMP backup register
/// offset: 0x14c
BKP19R: mmio.Mmio(packed struct(u32) {
/// BKP
BKP: u32 = 0x0,
}),
/// TAMP backup register
/// offset: 0x150
BKP20R: mmio.Mmio(packed struct(u32) {
/// BKP
BKP: u32 = 0x0,
}),
/// TAMP backup register
/// offset: 0x154
BKP21R: mmio.Mmio(packed struct(u32) {
/// BKP
BKP: u32 = 0x0,
}),
/// TAMP backup register
/// offset: 0x158
BKP22R: mmio.Mmio(packed struct(u32) {
/// BKP
BKP: u32 = 0x0,
}),
/// TAMP backup register
/// offset: 0x15c
BKP23R: mmio.Mmio(packed struct(u32) {
/// BKP
BKP: u32 = 0x0,
}),
/// TAMP backup register
/// offset: 0x160
BKP24R: mmio.Mmio(packed struct(u32) {
/// BKP
BKP: u32 = 0x0,
}),
/// TAMP backup register
/// offset: 0x164
BKP25R: mmio.Mmio(packed struct(u32) {
/// BKP
BKP: u32 = 0x0,
}),
/// TAMP backup register
/// offset: 0x168
BKP26R: mmio.Mmio(packed struct(u32) {
/// BKP
BKP: u32 = 0x0,
}),
/// TAMP backup register
/// offset: 0x16c
BKP27R: mmio.Mmio(packed struct(u32) {
/// BKP
BKP: u32 = 0x0,
}),
/// TAMP backup register
/// offset: 0x170
BKP28R: mmio.Mmio(packed struct(u32) {
/// BKP
BKP: u32 = 0x0,
}),
/// TAMP backup register
/// offset: 0x174
BKP29R: mmio.Mmio(packed struct(u32) {
/// BKP
BKP: u32 = 0x0,
}),
/// TAMP backup register
/// offset: 0x178
BKP30R: mmio.Mmio(packed struct(u32) {
/// BKP
BKP: u32 = 0x0,
}),
/// TAMP backup register
/// offset: 0x17c
BKP31R: mmio.Mmio(packed struct(u32) {
/// BKP
BKP: u32 = 0x0,
}),
};

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src/stm32g4/types/peripherals/TIM1.zig Normal file
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src/stm32g4/types/peripherals/TIM15.zig Normal file
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const microzig = @import("microzig");
const mmio = microzig.mmio;
const types = @import("../../types.zig");
/// General purpose timers
pub const TIM15 = extern struct {
/// TIM5 control register 1
/// offset: 0x00
TIM5_CR1: mmio.Mmio(packed struct(u16) {
/// Counter enable
CEN: enum(u1) {
/// Counter disabled
B_0x0 = 0x0,
/// Counter enabled
B_0x1 = 0x1,
} = .B_0x0,
/// Update disable
UDIS: enum(u1) {
/// UEV enabled.
B_0x0 = 0x0,
/// UEV disabled.
B_0x1 = 0x1,
} = .B_0x0,
/// Update request source
URS: enum(u1) {
/// Any of the following events generate an update interrupt or DMA request if enabled.
B_0x0 = 0x0,
/// Only counter overflow/underflow generates an update interrupt or DMA request if enabled.
B_0x1 = 0x1,
} = .B_0x0,
/// One-pulse mode
OPM: enum(u1) {
/// Counter is not stopped at update event
B_0x0 = 0x0,
/// Counter stops counting at the next update event (clearing the bit CEN)
B_0x1 = 0x1,
} = .B_0x0,
/// Direction
DIR: enum(u1) {
/// Counter used as upcounter
B_0x0 = 0x0,
/// Counter used as downcounter
B_0x1 = 0x1,
} = .B_0x0,
/// Center-aligned mode selection
CMS: enum(u2) {
/// Edge-aligned mode.
B_0x0 = 0x0,
/// Center-aligned mode 1.
B_0x1 = 0x1,
/// Center-aligned mode 2.
B_0x2 = 0x2,
/// Center-aligned mode 3.
B_0x3 = 0x3,
} = .B_0x0,
/// Auto-reload preload enable
ARPE: enum(u1) {
/// TIMx_ARR register is not buffered
B_0x0 = 0x0,
/// TIMx_ARR register is buffered
B_0x1 = 0x1,
} = .B_0x0,
/// Clock division
CKD: enum(u2) {
/// tless thansub>DTSless than/sub> = tless thansub>tim_ker_ckless than/sub>
B_0x0 = 0x0,
/// tless thansub>DTSless than/sub> = 2 tless thansub>tim_ker_ckless than/sub>
B_0x1 = 0x1,
/// tless thansub>DTSless than/sub> = 4 tless thansub>tim_ker_ckless than/sub>
B_0x2 = 0x2,
_,
} = .B_0x0,
reserved11: u1 = 0,
/// UIF status bit remapping
UIFREMAP: enum(u1) {
/// No remapping.
B_0x0 = 0x0,
/// Remapping enabled.
B_0x1 = 0x1,
} = .B_0x0,
/// Dithering Enable
DITHEN: enum(u1) {
/// Dithering disabled
B_0x0 = 0x0,
/// Dithering enabled
B_0x1 = 0x1,
} = .B_0x0,
padding: u3 = 0,
}),
/// offset: 0x02
reserved2: [2]u8,
/// TIM5 control register 2
/// offset: 0x04
TIM5_CR2: mmio.Mmio(packed struct(u32) {
reserved3: u3 = 0,
/// Capture/compare DMA selection
CCDS: enum(u1) {
/// CCx DMA request sent when CCx event occurs
B_0x0 = 0x0,
/// CCx DMA requests sent when update event occurs
B_0x1 = 0x1,
} = .B_0x0,
/// MMS[0]: Master mode selection
MMS: enum(u3) {
/// Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo).
B_0x0 = 0x0,
/// Enable - the Counter enable signal, CNT_EN, is used as trigger output (tim_trgo).
B_0x1 = 0x1,
/// Update - The update event is selected as trigger output (tim_trgo).
B_0x2 = 0x2,
/// Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred (tim_trgo).
B_0x3 = 0x3,
/// Compare - tim_oc1refc signal is used as trigger output (tim_trgo)
B_0x4 = 0x4,
/// Compare - tim_oc2refc signal is used as trigger output (tim_trgo)
B_0x5 = 0x5,
/// Compare - tim_oc3refc signal is used as trigger output (tim_trgo)
B_0x6 = 0x6,
/// Compare - tim_oc4refc signal is used as trigger output (tim_trgo)
B_0x7 = 0x7,
} = .B_0x0,
/// tim_ti1 selection
TI1S: enum(u1) {
/// The tim_ti1_in[15:0] multiplexer output is to tim_ti1 input
B_0x0 = 0x0,
/// The tim_ti1_in[15:0], tim_ti2_in[15:0] and tim_ti3_in[15:0] multiplexers outputs are XORed and connected to the tim_ti1 input.
B_0x1 = 0x1,
} = .B_0x0,
reserved25: u17 = 0,
/// MMS[3]
MMS_1: u1 = 0x0,
padding: u6 = 0,
}),
/// TIM5 slave mode control register
/// offset: 0x08
TIM5_SMCR: mmio.Mmio(packed struct(u32) {
/// SMS[0]: Slave mode selection
SMS: enum(u3) {
/// Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock.
B_0x0 = 0x0,
/// Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level.
B_0x1 = 0x1,
/// Encoder mode 2 - Counter counts up/down on tim_ti2fp2 edge depending on tim_ti1fp1 level.
B_0x2 = 0x2,
/// Encoder mode 3 - Counter counts up/down on both tim_ti1fp1 and tim_ti2fp2 edges depending on the level of the other input.
B_0x3 = 0x3,
/// Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers.
B_0x4 = 0x4,
/// Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high.
B_0x5 = 0x5,
/// Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset).
B_0x6 = 0x6,
/// External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter.
B_0x7 = 0x7,
} = .B_0x0,
/// OCREF clear selection
OCCS: enum(u1) {
/// tim_ocref_clr_int is connected to the tim_ocref_clr input
B_0x0 = 0x0,
/// tim_ocref_clr_int is connected to tim_etrf
B_0x1 = 0x1,
} = .B_0x0,
/// TS[0]: Trigger selection
TS: enum(u3) {
/// Internal trigger 0 (tim_itr0)
B_0x0 = 0x0,
/// Internal trigger 1 (tim_itr1)
B_0x1 = 0x1,
/// Internal trigger 2 (tim_itr2)
B_0x2 = 0x2,
/// Internal trigger 3 (tim_itr3)
B_0x3 = 0x3,
/// tim_ti1 edge detector (tim_ti1f_ed)
B_0x4 = 0x4,
/// Filtered timer input 1 (tim_ti1fp1)
B_0x5 = 0x5,
/// Filtered timer input 2 (tim_ti2fp2)
B_0x6 = 0x6,
/// External trigger input (tim_etrf)
B_0x7 = 0x7,
} = .B_0x0,
/// Master/Slave mode
MSM: enum(u1) {
/// No action
B_0x0 = 0x0,
/// The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo).
B_0x1 = 0x1,
} = .B_0x0,
/// External trigger filter
ETF: enum(u4) {
/// No filter, sampling is done at fless thansub>DTSless than/sub>
B_0x0 = 0x0,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2
B_0x1 = 0x1,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4
B_0x2 = 0x2,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8
B_0x3 = 0x3,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6
B_0x4 = 0x4,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8
B_0x5 = 0x5,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6
B_0x6 = 0x6,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8
B_0x7 = 0x7,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6
B_0x8 = 0x8,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8
B_0x9 = 0x9,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5
B_0xA = 0xa,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6
B_0xB = 0xb,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8
B_0xC = 0xc,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5
B_0xD = 0xd,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6
B_0xE = 0xe,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8
B_0xF = 0xf,
} = .B_0x0,
/// External trigger prescaler
ETPS: enum(u2) {
/// Prescaler OFF
B_0x0 = 0x0,
/// tim_etrp frequency divided by 2
B_0x1 = 0x1,
/// tim_etrp frequency divided by 4
B_0x2 = 0x2,
/// tim_etrp frequency divided by 8
B_0x3 = 0x3,
} = .B_0x0,
/// External clock enable
ECE: enum(u1) {
/// External clock mode 2 disabled
B_0x0 = 0x0,
/// External clock mode 2 enabled.
B_0x1 = 0x1,
} = .B_0x0,
/// External trigger polarity
ETP: enum(u1) {
/// tim_etr_in is non-inverted, active at high level or rising edge
B_0x0 = 0x0,
/// tim_etr_in is inverted, active at low level or falling edge
B_0x1 = 0x1,
} = .B_0x0,
/// SMS[3]
SMS_1: u1 = 0x0,
reserved20: u3 = 0,
/// TS[4:3]
TS_1: u2 = 0x0,
reserved24: u2 = 0,
/// SMS preload enable
SMSPE: enum(u1) {
/// SMS[3:0] bitfield is not preloaded
B_0x0 = 0x0,
/// SMS[3:0] preload is enabled
B_0x1 = 0x1,
} = .B_0x0,
/// SMS preload source
SMSPS: enum(u1) {
/// The transfer is triggered by the Timer's Update event
B_0x0 = 0x0,
/// The transfer is triggered by the Index event
B_0x1 = 0x1,
} = .B_0x0,
padding: u6 = 0,
}),
/// TIM5 DMA/Interrupt enable register
/// offset: 0x0c
TIM5_DIER: mmio.Mmio(packed struct(u32) {
/// Update interrupt enable
UIE: enum(u1) {
/// Update interrupt disabled.
B_0x0 = 0x0,
/// Update interrupt enabled.
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/Compare 1 interrupt enable
CC1IE: enum(u1) {
/// CC1 interrupt disabled.
B_0x0 = 0x0,
/// CC1 interrupt enabled.
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/Compare 2 interrupt enable
CC2IE: enum(u1) {
/// CC2 interrupt disabled.
B_0x0 = 0x0,
/// CC2 interrupt enabled.
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/Compare 3 interrupt enable
CC3IE: enum(u1) {
/// CC3 interrupt disabled.
B_0x0 = 0x0,
/// CC3 interrupt enabled.
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/Compare 4 interrupt enable
CC4IE: enum(u1) {
/// CC4 interrupt disabled.
B_0x0 = 0x0,
/// CC4 interrupt enabled.
B_0x1 = 0x1,
} = .B_0x0,
reserved6: u1 = 0,
/// Trigger interrupt enable
TIE: enum(u1) {
/// Trigger interrupt disabled.
B_0x0 = 0x0,
/// Trigger interrupt enabled.
B_0x1 = 0x1,
} = .B_0x0,
reserved8: u1 = 0,
/// Update DMA request enable
UDE: enum(u1) {
/// Update DMA request disabled.
B_0x0 = 0x0,
/// Update DMA request enabled.
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/Compare 1 DMA request enable
CC1DE: enum(u1) {
/// CC1 DMA request disabled.
B_0x0 = 0x0,
/// CC1 DMA request enabled.
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/Compare 2 DMA request enable
CC2DE: enum(u1) {
/// CC2 DMA request disabled.
B_0x0 = 0x0,
/// CC2 DMA request enabled.
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/Compare 3 DMA request enable
CC3DE: enum(u1) {
/// CC3 DMA request disabled.
B_0x0 = 0x0,
/// CC3 DMA request enabled.
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/Compare 4 DMA request enable
CC4DE: enum(u1) {
/// CC4 DMA request disabled.
B_0x0 = 0x0,
/// CC4 DMA request enabled.
B_0x1 = 0x1,
} = .B_0x0,
reserved14: u1 = 0,
/// Trigger DMA request enable
TDE: enum(u1) {
/// Trigger DMA request disabled.
B_0x0 = 0x0,
/// Trigger DMA request enabled.
B_0x1 = 0x1,
} = .B_0x0,
reserved20: u5 = 0,
/// Index interrupt enable
IDXIE: enum(u1) {
/// Index interrupt disabled
B_0x0 = 0x0,
/// Index interrupt enabled
B_0x1 = 0x1,
} = .B_0x0,
/// Direction change interrupt enable
DIRIE: enum(u1) {
/// Direction change interrupt disabled
B_0x0 = 0x0,
/// Direction change interrupt enabled
B_0x1 = 0x1,
} = .B_0x0,
/// Index error interrupt enable
IERRIE: enum(u1) {
/// Index error interrupt disabled
B_0x0 = 0x0,
/// Index error interrupt enabled
B_0x1 = 0x1,
} = .B_0x0,
/// Transition error interrupt enable
TERRIE: enum(u1) {
/// Transition error interrupt disabled
B_0x0 = 0x0,
/// Transition error interrupt enabled
B_0x1 = 0x1,
} = .B_0x0,
padding: u8 = 0,
}),
/// TIM5 status register
/// offset: 0x10
TIM5_SR: mmio.Mmio(packed struct(u32) {
/// Update interrupt flag
UIF: enum(u1) {
/// No update occurred
B_0x0 = 0x0,
/// Update interrupt pending.
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/compare 1 interrupt flag
CC1IF: enum(u1) {
/// No compare match / No input capture occurred
B_0x0 = 0x0,
/// A compare match or an input capture occurred
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/Compare 2 interrupt flag
CC2IF: u1 = 0x0,
/// Capture/Compare 3 interrupt flag
CC3IF: u1 = 0x0,
/// Capture/Compare 4 interrupt flag
CC4IF: u1 = 0x0,
reserved6: u1 = 0,
/// Trigger interrupt flag
TIF: enum(u1) {
/// No trigger event occurred.
B_0x0 = 0x0,
/// Trigger interrupt pending.
B_0x1 = 0x1,
} = .B_0x0,
reserved9: u2 = 0,
/// Capture/Compare 1 overcapture flag
CC1OF: enum(u1) {
/// No overcapture has been detected.
B_0x0 = 0x0,
/// The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/compare 2 overcapture flag
CC2OF: u1 = 0x0,
/// Capture/Compare 3 overcapture flag
CC3OF: u1 = 0x0,
/// Capture/Compare 4 overcapture flag
CC4OF: u1 = 0x0,
reserved20: u7 = 0,
/// Index interrupt flag
IDXF: enum(u1) {
/// No index event occurred.
B_0x0 = 0x0,
/// An index event has occurred
B_0x1 = 0x1,
} = .B_0x0,
/// Direction change interrupt flag
DIRF: enum(u1) {
/// No direction change
B_0x0 = 0x0,
/// Direction change
B_0x1 = 0x1,
} = .B_0x0,
/// Index error interrupt flag
IERRF: enum(u1) {
/// No index error has been detected.
B_0x0 = 0x0,
/// An index error has been detected
B_0x1 = 0x1,
} = .B_0x0,
/// Transition error interrupt flag
TERRF: enum(u1) {
/// No encoder transition error has been detected.
B_0x0 = 0x0,
/// An encoder transition error has been detected
B_0x1 = 0x1,
} = .B_0x0,
padding: u8 = 0,
}),
/// TIM5 event generation register
/// offset: 0x14
TIM5_EGR: mmio.Mmio(packed struct(u16) {
/// Update generation
UG: enum(u1) {
/// No action
B_0x0 = 0x0,
/// Re-initialize the counter and generates an update of the registers.
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/compare 1 generation
CC1G: enum(u1) {
/// No action
B_0x0 = 0x0,
/// A capture/compare event is generated on channel 1:
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/compare 2 generation
CC2G: u1 = 0x0,
/// Capture/compare 3 generation
CC3G: u1 = 0x0,
/// Capture/compare 4 generation
CC4G: u1 = 0x0,
reserved6: u1 = 0,
/// Trigger generation
TG: enum(u1) {
/// No action
B_0x0 = 0x0,
/// The TIF flag is set in TIMx_SR register.
B_0x1 = 0x1,
} = .B_0x0,
padding: u9 = 0,
}),
/// offset: 0x16
reserved22: [2]u8,
/// TIM5 capture/compare mode register 1 [alternate]
/// offset: 0x18
TIM5_CCMR1: mmio.Mmio(packed struct(u32) {
/// Capture/Compare 1 selection
CC1S: enum(u2) {
/// CC1 channel is configured as output
B_0x0 = 0x0,
/// CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1
B_0x1 = 0x1,
/// CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2
B_0x2 = 0x2,
/// CC1 channel is configured as input, tim_ic1 is mapped on tim_trc.
B_0x3 = 0x3,
} = .B_0x0,
/// Input capture 1 prescaler
IC1PSC: enum(u2) {
/// no prescaler, capture is done each time an edge is detected on the capture input
B_0x0 = 0x0,
/// capture is done once every 2 events
B_0x1 = 0x1,
/// capture is done once every 4 events
B_0x2 = 0x2,
/// capture is done once every 8 events
B_0x3 = 0x3,
} = .B_0x0,
/// Input capture 1 filter
IC1F: enum(u4) {
/// No filter, sampling is done at fless thansub>DTSless than/sub>
B_0x0 = 0x0,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2
B_0x1 = 0x1,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4
B_0x2 = 0x2,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8
B_0x3 = 0x3,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6
B_0x4 = 0x4,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8
B_0x5 = 0x5,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6
B_0x6 = 0x6,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8
B_0x7 = 0x7,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6
B_0x8 = 0x8,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8
B_0x9 = 0x9,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5
B_0xA = 0xa,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6
B_0xB = 0xb,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8
B_0xC = 0xc,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5
B_0xD = 0xd,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6
B_0xE = 0xe,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8
B_0xF = 0xf,
} = .B_0x0,
/// Capture/compare 2 selection
CC2S: enum(u2) {
/// CC2 channel is configured as output.
B_0x0 = 0x0,
/// CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2.
B_0x1 = 0x1,
/// CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1.
B_0x2 = 0x2,
/// CC2 channel is configured as input, tim_ic2 is mapped on tim_trc.
B_0x3 = 0x3,
} = .B_0x0,
/// Input capture 2 prescaler
IC2PSC: u2 = 0x0,
/// Input capture 2 filter
IC2F: u4 = 0x0,
padding: u16 = 0,
}),
/// TIM5 capture/compare mode register 2 [alternate]
/// offset: 0x1c
TIM5_CCMR2: mmio.Mmio(packed struct(u32) {
/// Capture/Compare 3 selection
CC3S: enum(u2) {
/// CC3 channel is configured as output
B_0x0 = 0x0,
/// CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3
B_0x1 = 0x1,
/// CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4
B_0x2 = 0x2,
/// CC3 channel is configured as input, tim_ic3 is mapped on tim_trc.
B_0x3 = 0x3,
} = .B_0x0,
/// Input capture 3 prescaler
IC3PSC: u2 = 0x0,
/// Input capture 3 filter
IC3F: u4 = 0x0,
/// Capture/Compare 4 selection
CC4S: enum(u2) {
/// CC4 channel is configured as output
B_0x0 = 0x0,
/// CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4
B_0x1 = 0x1,
/// CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3
B_0x2 = 0x2,
/// CC4 channel is configured as input, tim_ic4 is mapped on tim_trc.
B_0x3 = 0x3,
} = .B_0x0,
/// Input capture 4 prescaler
IC4PSC: u2 = 0x0,
/// Input capture 4 filter
IC4F: u4 = 0x0,
padding: u16 = 0,
}),
/// TIM5 capture/compare enable register
/// offset: 0x20
TIM5_CCER: mmio.Mmio(packed struct(u16) {
/// Capture/Compare 1 output enable.
CC1E: enum(u1) {
/// Capture mode disabled / OC1 is not active
B_0x0 = 0x0,
/// Capture mode enabled / OC1 signal is output on the corresponding output pin
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/Compare 1 output Polarity.
CC1P: enum(u1) {
/// OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)
B_0x0 = 0x0,
/// OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)
B_0x1 = 0x1,
} = .B_0x0,
reserved3: u1 = 0,
/// Capture/Compare 1 output Polarity.
CC1NP: u1 = 0x0,
/// Capture/Compare 2 output enable.
CC2E: u1 = 0x0,
/// Capture/Compare 2 output Polarity.
CC2P: u1 = 0x0,
reserved7: u1 = 0,
/// Capture/Compare 2 output Polarity.
CC2NP: u1 = 0x0,
/// Capture/Compare 3 output enable.
CC3E: u1 = 0x0,
/// Capture/Compare 3 output Polarity.
CC3P: u1 = 0x0,
reserved11: u1 = 0,
/// Capture/Compare 3 output Polarity.
CC3NP: u1 = 0x0,
/// Capture/Compare 4 output enable.
CC4E: u1 = 0x0,
/// Capture/Compare 4 output Polarity.
CC4P: u1 = 0x0,
reserved15: u1 = 0,
/// Capture/Compare 4 output Polarity.
CC4NP: u1 = 0x0,
}),
/// offset: 0x22
reserved34: [2]u8,
/// TIM5 counter
/// offset: 0x24
TIM5_CNT: mmio.Mmio(packed struct(u32) {
/// Least significant part of counter value
CNT: u31 = 0x0,
/// Value depends on IUFREMAP in TIMx_CR1.
UIFCPY_CNT: u1 = 0x0,
}),
/// TIM5 prescaler
/// offset: 0x28
TIM5_PSC: mmio.Mmio(packed struct(u16) {
/// Prescaler value
PSC: u16 = 0x0,
}),
/// offset: 0x2a
reserved42: [2]u8,
/// TIM5 auto-reload register
/// offset: 0x2c
TIM5_ARR: mmio.Mmio(packed struct(u32) {
/// Auto-reload value
ARR: u32 = 0xFFFFFFFF,
}),
/// offset: 0x30
reserved48: [4]u8,
/// TIM5 capture/compare register 1
/// offset: 0x34
TIM5_CCR1: mmio.Mmio(packed struct(u32) {
/// Capture/compare 1 value
CCR1: u32 = 0x0,
}),
/// TIM5 capture/compare register 2
/// offset: 0x38
TIM5_CCR2: mmio.Mmio(packed struct(u32) {
/// Capture/compare 2 value
CCR2: u32 = 0x0,
}),
/// TIM5 capture/compare register 3
/// offset: 0x3c
TIM5_CCR3: mmio.Mmio(packed struct(u32) {
/// Capture/compare 3 value
CCR3: u32 = 0x0,
}),
/// TIM5 capture/compare register 4
/// offset: 0x40
TIM5_CCR4: mmio.Mmio(packed struct(u32) {
/// Capture/compare 4 value
CCR4: u32 = 0x0,
}),
/// offset: 0x44
reserved68: [20]u8,
/// TIM5 timer encoder control register
/// offset: 0x58
TIM5_ECR: mmio.Mmio(packed struct(u32) {
/// Index enable
IE: enum(u1) {
/// Index disabled
B_0x0 = 0x0,
/// Index enabled
B_0x1 = 0x1,
} = .B_0x0,
/// Index direction
IDIR: enum(u2) {
/// Index resets the counter whatever the direction
B_0x0 = 0x0,
/// Index resets the counter when up-counting only
B_0x1 = 0x1,
/// Index resets the counter when down-counting only
B_0x2 = 0x2,
_,
} = .B_0x0,
reserved5: u2 = 0,
/// First index
FIDX: enum(u1) {
/// Index is always active
B_0x0 = 0x0,
/// the first Index only resets the counter
B_0x1 = 0x1,
} = .B_0x0,
/// Index positioning
IPOS: enum(u2) {
/// Index resets the counter when AB = 00
B_0x0 = 0x0,
/// Index resets the counter when AB = 01
B_0x1 = 0x1,
/// Index resets the counter when AB = 10
B_0x2 = 0x2,
/// Index resets the counter when AB = 11
B_0x3 = 0x3,
} = .B_0x0,
reserved16: u8 = 0,
/// Pulse width
PW: u8 = 0x0,
/// Pulse width prescaler
PWPRSC: u3 = 0x0,
padding: u5 = 0,
}),
/// TIM5 timer input selection register
/// offset: 0x5c
TIM5_TISEL: mmio.Mmio(packed struct(u32) {
/// Selects tim_ti1[15:0] input
TI1SEL: enum(u4) {
/// tim_ti1_in0: TIMx_CH1
B_0x0 = 0x0,
/// tim_ti1_in1
B_0x1 = 0x1,
/// tim_ti1_in15
B_0xF = 0xf,
_,
} = .B_0x0,
reserved8: u4 = 0,
/// Selects tim_ti2[15:0] input
TI2SEL: enum(u4) {
/// tim_ti2_in0: TIMx_CH2
B_0x0 = 0x0,
/// tim_ti2_in1
B_0x1 = 0x1,
/// tim_ti2_in15
B_0xF = 0xf,
_,
} = .B_0x0,
reserved16: u4 = 0,
/// Selects tim_ti3[15:0] input
TI3SEL: enum(u4) {
/// tim_ti3_in0: TIMx_CH3
B_0x0 = 0x0,
/// tim_ti3_in1
B_0x1 = 0x1,
/// tim_ti3_in15
B_0xF = 0xf,
_,
} = .B_0x0,
reserved24: u4 = 0,
/// Selects tim_ti4[15:0] input
TI4SEL: enum(u4) {
/// tim_ti4_in0: TIMx_CH4
B_0x0 = 0x0,
/// tim_ti4_in1
B_0x1 = 0x1,
/// tim_ti4_in15
B_0xF = 0xf,
_,
} = .B_0x0,
padding: u4 = 0,
}),
/// TIM5 alternate function register 1
/// offset: 0x60
TIM5_AF1: mmio.Mmio(packed struct(u32) {
reserved14: u14 = 0,
/// etr_in source selection
ETRSEL: enum(u4) {
/// tim_etr0: TIMx_ETR input
B_0x0 = 0x0,
/// tim_etr1
B_0x1 = 0x1,
/// tim_etr15
B_0xF = 0xf,
_,
} = .B_0x0,
padding: u14 = 0,
}),
/// TIM5 alternate function register 2
/// offset: 0x64
TIM5_AF2: mmio.Mmio(packed struct(u32) {
reserved16: u16 = 0,
/// ocref_clr source selection
OCRSEL: enum(u3) {
/// tim_ocref_clr0
B_0x0 = 0x0,
/// tim_ocref_clr1
B_0x1 = 0x1,
/// tim_ocref_clr7
B_0x7 = 0x7,
_,
} = .B_0x0,
padding: u13 = 0,
}),
/// offset: 0x68
reserved104: [884]u8,
/// TIM5 DMA control register
/// offset: 0x3dc
TIM5_DCR: mmio.Mmio(packed struct(u32) {
/// DMA base address
DBA: enum(u5) {
/// TIMx_CR1,
B_0x0 = 0x0,
/// TIMx_CR2,
B_0x1 = 0x1,
/// TIMx_SMCR,
B_0x2 = 0x2,
_,
} = .B_0x0,
reserved8: u3 = 0,
/// DMA burst length
DBL: enum(u5) {
/// 1 transfer
B_0x0 = 0x0,
/// 2 transfers
B_0x1 = 0x1,
/// 3 transfers
B_0x2 = 0x2,
/// 26 transfers
B_0x1A = 0x1a,
_,
} = .B_0x0,
padding: u19 = 0,
}),
/// TIM5 DMA address for full transfer
/// offset: 0x3e0
TIM5_DMAR: mmio.Mmio(packed struct(u32) {
/// DMA register for burst accesses
DMAB: u32 = 0x0,
}),
};

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src/stm32g4/types/peripherals/TIM16.zig Normal file
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const microzig = @import("microzig");
const mmio = microzig.mmio;
const types = @import("../../types.zig");
/// General purpose timers
pub const TIM16 = extern struct {
/// TIM16 control register 1
/// offset: 0x00
TIM16_CR1: mmio.Mmio(packed struct(u16) {
/// Counter enable
CEN: enum(u1) {
/// Counter disabled
B_0x0 = 0x0,
/// Counter enabled
B_0x1 = 0x1,
} = .B_0x0,
/// Update disable
UDIS: enum(u1) {
/// UEV enabled.
B_0x0 = 0x0,
/// UEV disabled.
B_0x1 = 0x1,
} = .B_0x0,
/// Update request source
URS: enum(u1) {
/// Any of the following events generate an update interrupt or DMA request if enabled.
B_0x0 = 0x0,
/// nly counter overflow/underflow generates an update interrupt or DMA request if enabled.
B_0x1 = 0x1,
} = .B_0x0,
/// One pulse mode
OPM: enum(u1) {
/// Counter is not stopped at update event
B_0x0 = 0x0,
/// Counter stops counting at the next update event (clearing the bit CEN)
B_0x1 = 0x1,
} = .B_0x0,
reserved7: u3 = 0,
/// Auto-reload preload enable
ARPE: enum(u1) {
/// TIMx_ARR register is not buffered
B_0x0 = 0x0,
/// TIMx_ARR register is buffered
B_0x1 = 0x1,
} = .B_0x0,
/// Clock division
CKD: enum(u2) {
/// tless thansub>DTSless than/sub>=tless thansub>tim_ker_ckless than/sub>
B_0x0 = 0x0,
/// tless thansub>DTSless than/sub>=2*tless thansub>tim_ker_ckless than/sub>
B_0x1 = 0x1,
/// tless thansub>DTSless than/sub>=4*tless thansub>tim_ker_ckless than/sub>
B_0x2 = 0x2,
_,
} = .B_0x0,
reserved11: u1 = 0,
/// UIF status bit remapping
UIFREMAP: enum(u1) {
/// No remapping.
B_0x0 = 0x0,
/// Remapping enabled.
B_0x1 = 0x1,
} = .B_0x0,
/// Dithering enable
DITHEN: enum(u1) {
/// Dithering disabled
B_0x0 = 0x0,
/// Dithering enabled
B_0x1 = 0x1,
} = .B_0x0,
padding: u3 = 0,
}),
/// offset: 0x02
reserved2: [2]u8,
/// TIM16 control register 2
/// offset: 0x04
TIM16_CR2: mmio.Mmio(packed struct(u16) {
/// Capture/compare preloaded control
CCPC: enum(u1) {
/// CCxE, CCxNE and OCxM bits are not preloaded
B_0x0 = 0x0,
/// CCxE, CCxNE and OCxM bits are preloaded, after having been written, they are updated only when COM bit is set.
B_0x1 = 0x1,
} = .B_0x0,
reserved2: u1 = 0,
/// Capture/compare control update selection
CCUS: enum(u1) {
/// When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit only.
B_0x0 = 0x0,
/// When capture/compare control bits are preloaded (CCPC=1), they are updated by setting the COMG bit or when a rising edge occurs on tim_trgi (if available).
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/compare DMA selection
CCDS: enum(u1) {
/// CCx DMA request sent when CCx event occurs
B_0x0 = 0x0,
/// CCx DMA requests sent when update event occurs
B_0x1 = 0x1,
} = .B_0x0,
reserved8: u4 = 0,
/// Output Idle state 1 (tim_oc1 output)
OIS1: enum(u1) {
/// tim_oc1=0 after a dead-time when MOE=0
B_0x0 = 0x0,
/// tim_oc1=1 after a dead-time when MOE=0
B_0x1 = 0x1,
} = .B_0x0,
/// Output Idle state 1 (tim_oc1n output)
OIS1N: enum(u1) {
/// tim_oc1n=0 after a dead-time when MOE=0
B_0x0 = 0x0,
/// tim_oc1n=1 after a dead-time when MOE=0
B_0x1 = 0x1,
} = .B_0x0,
padding: u6 = 0,
}),
/// offset: 0x06
reserved6: [6]u8,
/// TIM16 DMA/interrupt enable register
/// offset: 0x0c
TIM16_DIER: mmio.Mmio(packed struct(u16) {
/// Update interrupt enable
UIE: enum(u1) {
/// Update interrupt disabled
B_0x0 = 0x0,
/// Update interrupt enabled
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/Compare 1 interrupt enable
CC1IE: enum(u1) {
/// CC1 interrupt disabled
B_0x0 = 0x0,
/// CC1 interrupt enabled
B_0x1 = 0x1,
} = .B_0x0,
reserved5: u3 = 0,
/// COM interrupt enable
COMIE: enum(u1) {
/// COM interrupt disabled
B_0x0 = 0x0,
/// COM interrupt enabled
B_0x1 = 0x1,
} = .B_0x0,
reserved7: u1 = 0,
/// Break interrupt enable
BIE: enum(u1) {
/// Break interrupt disabled
B_0x0 = 0x0,
/// Break interrupt enabled
B_0x1 = 0x1,
} = .B_0x0,
/// Update DMA request enable
UDE: enum(u1) {
/// Update DMA request disabled
B_0x0 = 0x0,
/// Update DMA request enabled
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/Compare 1 DMA request enable
CC1DE: enum(u1) {
/// CC1 DMA request disabled
B_0x0 = 0x0,
/// CC1 DMA request enabled
B_0x1 = 0x1,
} = .B_0x0,
padding: u6 = 0,
}),
/// offset: 0x0e
reserved14: [2]u8,
/// TIM16 status register
/// offset: 0x10
TIM16_SR: mmio.Mmio(packed struct(u16) {
/// Update interrupt flag
UIF: enum(u1) {
/// No update occurred.
B_0x0 = 0x0,
/// Update interrupt pending.
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/Compare 1 interrupt flag
CC1IF: enum(u1) {
/// No compare match / No input capture occurred
B_0x0 = 0x0,
/// A compare match or an input capture occurred
B_0x1 = 0x1,
} = .B_0x0,
reserved5: u3 = 0,
/// COM interrupt flag
COMIF: enum(u1) {
/// No COM event occurred
B_0x0 = 0x0,
/// COM interrupt pending
B_0x1 = 0x1,
} = .B_0x0,
reserved7: u1 = 0,
/// Break interrupt flag
BIF: enum(u1) {
/// No break event occurred
B_0x0 = 0x0,
/// An active level has been detected on the break input
B_0x1 = 0x1,
} = .B_0x0,
reserved9: u1 = 0,
/// Capture/Compare 1 overcapture flag
CC1OF: enum(u1) {
/// No overcapture has been detected
B_0x0 = 0x0,
/// The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set
B_0x1 = 0x1,
} = .B_0x0,
padding: u6 = 0,
}),
/// offset: 0x12
reserved18: [2]u8,
/// TIM16 event generation register
/// offset: 0x14
TIM16_EGR: mmio.Mmio(packed struct(u16) {
/// Update generation
UG: enum(u1) {
/// No action.
B_0x0 = 0x0,
/// Reinitialize the counter and generates an update of the registers.
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/Compare 1 generation
CC1G: enum(u1) {
/// No action.
B_0x0 = 0x0,
/// A capture/compare event is generated on channel 1:
B_0x1 = 0x1,
} = .B_0x0,
reserved5: u3 = 0,
/// Capture/Compare control update generation
COMG: enum(u1) {
/// No action
B_0x0 = 0x0,
/// When the CCPC bit is set, it is possible to update the CCxE, CCxNE and OCxM bits
B_0x1 = 0x1,
} = .B_0x0,
reserved7: u1 = 0,
/// Break generation
BG: enum(u1) {
/// No action.
B_0x0 = 0x0,
/// A break event is generated.
B_0x1 = 0x1,
} = .B_0x0,
padding: u8 = 0,
}),
/// offset: 0x16
reserved22: [2]u8,
/// TIM16 capture/compare mode register 1
/// offset: 0x18
TIM16_CCMR1: mmio.Mmio(packed struct(u32) {
/// Capture/Compare 1 selection
CC1S: enum(u2) {
/// CC1 channel is configured as output
B_0x0 = 0x0,
/// CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1
B_0x1 = 0x1,
_,
} = .B_0x0,
/// Input capture 1 prescaler
IC1PSC: enum(u2) {
/// no prescaler, capture is done each time an edge is detected on the capture input.
B_0x0 = 0x0,
/// capture is done once every 2 events
B_0x1 = 0x1,
/// capture is done once every 4 events
B_0x2 = 0x2,
/// capture is done once every 8 events
B_0x3 = 0x3,
} = .B_0x0,
/// Input capture 1 filter
IC1F: enum(u4) {
/// No filter, sampling is done at fless thansub>DTSless than/sub>
B_0x0 = 0x0,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2
B_0x1 = 0x1,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4
B_0x2 = 0x2,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8
B_0x3 = 0x3,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=
B_0x4 = 0x4,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8
B_0x5 = 0x5,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6
B_0x6 = 0x6,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8
B_0x7 = 0x7,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6
B_0x8 = 0x8,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8
B_0x9 = 0x9,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5
B_0xA = 0xa,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6
B_0xB = 0xb,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8
B_0xC = 0xc,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5
B_0xD = 0xd,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6
B_0xE = 0xe,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8
B_0xF = 0xf,
} = .B_0x0,
padding: u24 = 0,
}),
/// offset: 0x1c
reserved28: [4]u8,
/// TIM16 capture/compare enable register
/// offset: 0x20
TIM16_CCER: mmio.Mmio(packed struct(u16) {
/// Capture/Compare 1 output enable
CC1E: enum(u1) {
/// Capture mode disabled / OC1 is not active (see below)
B_0x0 = 0x0,
/// Capture mode enabled / OC1 signal is output on the corresponding output pin
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/Compare 1 output polarity
CC1P: enum(u1) {
/// OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)
B_0x0 = 0x0,
/// OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/Compare 1 complementary output enable
CC1NE: enum(u1) {
/// Off - tim_oc1n is not active.
B_0x0 = 0x0,
/// On - tim_oc1n signal is output on the corresponding output pin depending on MOE, OSSI, OSSR, OIS1, OIS1N and CC1E bits.
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/Compare 1 complementary output polarity
CC1NP: enum(u1) {
/// tim_oc1n active high
B_0x0 = 0x0,
/// tim_oc1n active low
B_0x1 = 0x1,
} = .B_0x0,
padding: u12 = 0,
}),
/// offset: 0x22
reserved34: [2]u8,
/// TIM16 counter
/// offset: 0x24
TIM16_CNT: mmio.Mmio(packed struct(u32) {
/// Counter value
CNT: u16 = 0x0,
reserved31: u15 = 0,
/// UIF Copy
UIFCPY: u1 = 0x0,
}),
/// TIM16 prescaler
/// offset: 0x28
TIM16_PSC: mmio.Mmio(packed struct(u16) {
/// Prescaler value
PSC: u16 = 0x0,
}),
/// offset: 0x2a
reserved42: [2]u8,
/// TIM16 auto-reload register
/// offset: 0x2c
TIM16_ARR: mmio.Mmio(packed struct(u32) {
/// Auto-reload value
ARR: u20 = 0xFFFF,
padding: u12 = 0,
}),
/// TIM16 repetition counter register
/// offset: 0x30
TIM16_RCR: mmio.Mmio(packed struct(u16) {
/// Repetition counter reload value
REP: u8 = 0x0,
padding: u8 = 0,
}),
/// offset: 0x32
reserved50: [2]u8,
/// TIM16 capture/compare register 1
/// offset: 0x34
TIM16_CCR1: mmio.Mmio(packed struct(u32) {
/// Capture/Compare 1 value
CCR1: u20 = 0x0,
padding: u12 = 0,
}),
/// offset: 0x38
reserved56: [12]u8,
/// TIM16 break and dead-time register
/// offset: 0x44
TIM16_BDTR: mmio.Mmio(packed struct(u32) {
/// Dead-time generator setup
DTG: u8 = 0x0,
/// Lock configuration
LOCK: enum(u2) {
/// LOCK OFF - No bit is write protected
B_0x0 = 0x0,
/// LOCK Level 1 = DTG bits in TIMx_BDTR register, OISx and OISxN bits in TIMx_CR2 register and BKBID/BKE/BKP/AOE bits in TIMx_BDTR register can no longer be written.
B_0x1 = 0x1,
/// LOCK Level 2 = LOCK Level 1 + CC Polarity bits (CCxP/CCxNP bits in TIMx_CCER register, as long as the related channel is configured in output through the CCxS bits) as well as OSSR and OSSI bits can no longer be written.
B_0x2 = 0x2,
/// LOCK Level 3 = LOCK Level 2 + CC Control bits (OCxM and OCxPE bits in TIMx_CCMRx registers, as long as the related channel is configured in output through the CCxS bits) can no longer be written.
B_0x3 = 0x3,
} = .B_0x0,
/// Off-state selection for Idle mode
OSSI: enum(u1) {
/// When inactive, tim_oc1/tim_oc1n outputs are disabled (tim_oc1/tim_oc1n enable output signal=0)
B_0x0 = 0x0,
/// When inactive, tim_oc1/tim_oc1n outputs are forced first with their idle level as soon as CC1E=1 or CC1NE=1.
B_0x1 = 0x1,
} = .B_0x0,
/// Off-state selection for Run mode
OSSR: enum(u1) {
/// When inactive, tim_oc1/tim_oc1n outputs are disabled (the timer releases the output control which is taken over by the GPIO, which forces a Hi-Z state)
B_0x0 = 0x0,
/// When inactive, tim_oc1/tim_oc1n outputs are enabled with their inactive level as soon as CC1E=1 or CC1NE=1 (the output is still controlled by the timer).
B_0x1 = 0x1,
} = .B_0x0,
/// Break enable
BKE: enum(u1) {
/// Break inputs (tim_brk and tim_sys_brk event) disabled
B_0x0 = 0x0,
_,
} = .B_0x0,
/// Break polarity
BKP: enum(u1) {
/// Break input tim_brk is active low
B_0x0 = 0x0,
/// Break input tim_brk is active high
B_0x1 = 0x1,
} = .B_0x0,
/// Automatic output enable
AOE: enum(u1) {
/// MOE can be set only by software
B_0x0 = 0x0,
/// MOE can be set by software or automatically at the next update event (if the tim_brk input is not active)
B_0x1 = 0x1,
} = .B_0x0,
/// Main output enable
MOE: enum(u1) {
/// tim_oc1 and tim_oc1n outputs are disabled or forced to idle state depending on the OSSI bit.
B_0x0 = 0x0,
/// tim_oc1 and tim_oc1n outputs are enabled if their respective enable bits are set (CC1E, CC1NE in TIMx_CCER register)
B_0x1 = 0x1,
} = .B_0x0,
/// Break filter
BKF: enum(u4) {
/// No filter, tim_brk acts asynchronously
B_0x0 = 0x0,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2
B_0x1 = 0x1,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4
B_0x2 = 0x2,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8
B_0x3 = 0x3,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6
B_0x4 = 0x4,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8
B_0x5 = 0x5,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6
B_0x6 = 0x6,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8
B_0x7 = 0x7,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6
B_0x8 = 0x8,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8
B_0x9 = 0x9,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5
B_0xA = 0xa,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6
B_0xB = 0xb,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8
B_0xC = 0xc,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5
B_0xD = 0xd,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6
B_0xE = 0xe,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8
B_0xF = 0xf,
} = .B_0x0,
reserved26: u6 = 0,
/// Break Disarm
BKDSRM: enum(u1) {
/// Break input tim_brk is armed
B_0x0 = 0x0,
/// Break input tim_brk is disarmed
B_0x1 = 0x1,
} = .B_0x0,
reserved28: u1 = 0,
/// Break Bidirectional
BKBID: enum(u1) {
/// Break input tim_brk in input mode
B_0x0 = 0x0,
/// Break input tim_brk in bidirectional mode
B_0x1 = 0x1,
} = .B_0x0,
padding: u3 = 0,
}),
/// offset: 0x48
reserved72: [12]u8,
/// TIM16 timer deadtime register 2
/// offset: 0x54
TIM16_DTR2: mmio.Mmio(packed struct(u32) {
/// Dead-time falling edge generator setup
DTGF: u8 = 0x0,
reserved16: u8 = 0,
/// Deadtime asymmetric enable
DTAE: enum(u1) {
/// Deadtime on rising and falling edges are identical, and defined with DTG[7:0] register
B_0x0 = 0x0,
/// Deadtime on rising edge is defined with DTG[7:0] register and deadtime on falling edge is defined with DTGF[7:0] bits.
B_0x1 = 0x1,
} = .B_0x0,
/// Deadtime preload enable
DTPE: enum(u1) {
/// Deadtime value is not preloaded
B_0x0 = 0x0,
/// Deadtime value preload is enabled
B_0x1 = 0x1,
} = .B_0x0,
padding: u14 = 0,
}),
/// offset: 0x58
reserved88: [4]u8,
/// TIM16 input selection register
/// offset: 0x5c
TIM16_TISEL: mmio.Mmio(packed struct(u32) {
/// selects tim_ti1_in[15:0] input
TI1SEL: enum(u4) {
/// TIMx_CH1 input (tim_ti1_in0)
B_0x0 = 0x0,
/// tim_ti1_in1
B_0x1 = 0x1,
/// tim_ti1_in15
B_0xF = 0xf,
_,
} = .B_0x0,
padding: u28 = 0,
}),
/// TIM16 alternate function register 1
/// offset: 0x60
TIM16_AF1: mmio.Mmio(packed struct(u32) {
/// TIMx_BKIN input enable
BKINE: enum(u1) {
/// TIMx_BKIN input disabled
B_0x0 = 0x0,
/// TIMx_BKIN input enabled
B_0x1 = 0x1,
} = .B_0x1,
/// tim_brk_cmp1 enable
BKCMP1E: enum(u1) {
/// tim_brk_cmp1 input disabled
B_0x0 = 0x0,
/// tim_brk_cmp1 input enabled
B_0x1 = 0x1,
} = .B_0x0,
/// tim_brk_cmp2 enable
BKCMP2E: enum(u1) {
/// tim_brk_cmp2 input disabled
B_0x0 = 0x0,
/// tim_brk_cmp2 input enabled
B_0x1 = 0x1,
} = .B_0x0,
/// tim_brk_cmp3 enable
BKCMP3E: enum(u1) {
/// tim_brk_cmp3 input disabled
B_0x0 = 0x0,
/// tim_brk_cmp3 input enabled
B_0x1 = 0x1,
} = .B_0x0,
/// tim_brk_cmp4 enable
BKCMP4E: enum(u1) {
/// tim_brk_cmp4 input disabled
B_0x0 = 0x0,
/// tim_brk_cmp4 input enabled
B_0x1 = 0x1,
} = .B_0x0,
/// tim_brk_cmp5 enable
BKCMP5E: enum(u1) {
/// tim_brk_cmp5 input disabled
B_0x0 = 0x0,
/// tim_brk_cmp5 input enabled
B_0x1 = 0x1,
} = .B_0x0,
/// tim_brk_cmp6 enable
BKCMP6E: enum(u1) {
/// tim_brk_cmp6 input disabled
B_0x0 = 0x0,
/// tim_brk_cmp6 input enabled
B_0x1 = 0x1,
} = .B_0x0,
/// tim_brk_cmp7 enable
BKCMP7E: enum(u1) {
/// tim_brk_cmp7 input disabled
B_0x0 = 0x0,
/// tim_brk_cmp7 input enabled
B_0x1 = 0x1,
} = .B_0x0,
/// tim_brk_cmp8 enable
BKCMP8E: enum(u1) {
/// tim_brk_cmp8 input disabled
B_0x0 = 0x0,
/// tim_brk_cmp8 input enabled
B_0x1 = 0x1,
} = .B_0x0,
/// TIMx_BKIN input polarity
BKINP: enum(u1) {
/// TIMx_BKIN input is active high
B_0x0 = 0x0,
/// TIMx_BKIN input is active low
B_0x1 = 0x1,
} = .B_0x0,
/// tim_brk_cmp1 input polarity
BKCMP1P: enum(u1) {
/// tim_brk_cmp1 input is active high
B_0x0 = 0x0,
/// tim_brk_cmp1 input is active low
B_0x1 = 0x1,
} = .B_0x0,
/// tim_brk_cmp2 input polarity
BKCMP2P: enum(u1) {
/// tim_brk_cmp2 input is active high
B_0x0 = 0x0,
/// tim_brk_cmp2 input is active low
B_0x1 = 0x1,
} = .B_0x0,
/// tim_brk_cmp3 input polarity
BKCMP3P: enum(u1) {
/// tim_brk_cmp3 input is active high
B_0x0 = 0x0,
/// tim_brk_cmp3 input is active low
B_0x1 = 0x1,
} = .B_0x0,
/// tim_brk_cmp4 input polarity
BKCMP4P: enum(u1) {
/// tim_brk_cmp4 input is active high
B_0x0 = 0x0,
/// tim_brk_cmp4 input is active low
B_0x1 = 0x1,
} = .B_0x0,
padding: u18 = 0,
}),
/// TIM16 alternate function register 2
/// offset: 0x64
TIM16_AF2: mmio.Mmio(packed struct(u32) {
reserved16: u16 = 0,
/// tim_ocref_clr source selection
OCRSEL: enum(u3) {
/// tim_ocref_clr0
B_0x0 = 0x0,
/// tim_ocref_clr1
B_0x1 = 0x1,
/// tim_ocref_clr2
B_0x2 = 0x2,
/// tim_ocref_clr3
B_0x3 = 0x3,
/// tim_ocref_clr4
B_0x4 = 0x4,
/// tim_ocref_clr5
B_0x5 = 0x5,
/// tim_ocref_clr6
B_0x6 = 0x6,
/// tim_ocref_clr7
B_0x7 = 0x7,
} = .B_0x0,
padding: u13 = 0,
}),
/// TIM16 option register 1
/// offset: 0x68
TIM16_OR1: mmio.Mmio(packed struct(u32) {
/// HSE Divided by 32 enable
HSE32EN: enum(u1) {
/// HSE divided by 32 disabled
B_0x0 = 0x0,
/// HSE divided by 32 enabled
B_0x1 = 0x1,
} = .B_0x0,
padding: u31 = 0,
}),
/// offset: 0x6c
reserved108: [880]u8,
/// TIM16 DMA control register
/// offset: 0x3dc
TIM16_DCR: mmio.Mmio(packed struct(u32) {
/// DMA base address
DBA: enum(u5) {
/// TIMx_CR1,
B_0x0 = 0x0,
/// TIMx_CR2,
B_0x1 = 0x1,
/// TIMx_SMCR,
B_0x2 = 0x2,
_,
} = .B_0x0,
reserved8: u3 = 0,
/// DMA burst length
DBL: enum(u5) {
/// 1 transfer,
B_0x0 = 0x0,
/// 2 transfers,
B_0x1 = 0x1,
/// 3 transfers,
B_0x2 = 0x2,
/// 18 transfers.
B_0x11 = 0x11,
_,
} = .B_0x0,
padding: u19 = 0,
}),
/// TIM16/TIM17 DMA address for full transfer
/// offset: 0x3e0
TIM16_DMAR: mmio.Mmio(packed struct(u32) {
/// DMA register for burst accesses
DMAB: u32 = 0x0,
}),
};

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src/stm32g4/types/peripherals/TIM2.zig Normal file
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const microzig = @import("microzig");
const mmio = microzig.mmio;
const types = @import("../../types.zig");
/// Advanced-timers
pub const TIM2 = extern struct {
/// TIM2 control register 1
/// offset: 0x00
TIM2_CR1: mmio.Mmio(packed struct(u16) {
/// Counter enable
CEN: enum(u1) {
/// Counter disabled
B_0x0 = 0x0,
/// Counter enabled
B_0x1 = 0x1,
} = .B_0x0,
/// Update disable
UDIS: enum(u1) {
/// UEV enabled.
B_0x0 = 0x0,
/// UEV disabled.
B_0x1 = 0x1,
} = .B_0x0,
/// Update request source
URS: enum(u1) {
/// Any of the following events generate an update interrupt or DMA request if enabled.
B_0x0 = 0x0,
/// Only counter overflow/underflow generates an update interrupt or DMA request if enabled.
B_0x1 = 0x1,
} = .B_0x0,
/// One-pulse mode
OPM: enum(u1) {
/// Counter is not stopped at update event
B_0x0 = 0x0,
/// Counter stops counting at the next update event (clearing the bit CEN)
B_0x1 = 0x1,
} = .B_0x0,
/// Direction
DIR: enum(u1) {
/// Counter used as upcounter
B_0x0 = 0x0,
/// Counter used as downcounter
B_0x1 = 0x1,
} = .B_0x0,
/// Center-aligned mode selection
CMS: enum(u2) {
/// Edge-aligned mode.
B_0x0 = 0x0,
/// Center-aligned mode 1.
B_0x1 = 0x1,
/// Center-aligned mode 2.
B_0x2 = 0x2,
/// Center-aligned mode 3.
B_0x3 = 0x3,
} = .B_0x0,
/// Auto-reload preload enable
ARPE: enum(u1) {
/// TIMx_ARR register is not buffered
B_0x0 = 0x0,
/// TIMx_ARR register is buffered
B_0x1 = 0x1,
} = .B_0x0,
/// Clock division
CKD: enum(u2) {
/// tless thansub>DTSless than/sub> = tless thansub>tim_ker_ckless than/sub>
B_0x0 = 0x0,
/// tless thansub>DTSless than/sub> = 2 tless thansub>tim_ker_ckless than/sub>
B_0x1 = 0x1,
/// tless thansub>DTSless than/sub> = 4 tless thansub>tim_ker_ckless than/sub>
B_0x2 = 0x2,
_,
} = .B_0x0,
reserved11: u1 = 0,
/// UIF status bit remapping
UIFREMAP: enum(u1) {
/// No remapping.
B_0x0 = 0x0,
/// Remapping enabled.
B_0x1 = 0x1,
} = .B_0x0,
/// Dithering Enable
DITHEN: enum(u1) {
/// Dithering disabled
B_0x0 = 0x0,
/// Dithering enabled
B_0x1 = 0x1,
} = .B_0x0,
padding: u3 = 0,
}),
/// offset: 0x02
reserved2: [2]u8,
/// TIM2 control register 2
/// offset: 0x04
TIM2_CR2: mmio.Mmio(packed struct(u32) {
reserved3: u3 = 0,
/// Capture/compare DMA selection
CCDS: enum(u1) {
/// CCx DMA request sent when CCx event occurs
B_0x0 = 0x0,
/// CCx DMA requests sent when update event occurs
B_0x1 = 0x1,
} = .B_0x0,
/// MMS[0]: Master mode selection
MMS: enum(u3) {
/// Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo).
B_0x0 = 0x0,
/// Enable - the Counter enable signal, CNT_EN, is used as trigger output (tim_trgo).
B_0x1 = 0x1,
/// Update - The update event is selected as trigger output (tim_trgo).
B_0x2 = 0x2,
/// Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred (tim_trgo).
B_0x3 = 0x3,
/// Compare - tim_oc1refc signal is used as trigger output (tim_trgo)
B_0x4 = 0x4,
/// Compare - tim_oc2refc signal is used as trigger output (tim_trgo)
B_0x5 = 0x5,
/// Compare - tim_oc3refc signal is used as trigger output (tim_trgo)
B_0x6 = 0x6,
/// Compare - tim_oc4refc signal is used as trigger output (tim_trgo)
B_0x7 = 0x7,
} = .B_0x0,
/// tim_ti1 selection
TI1S: enum(u1) {
/// The tim_ti1_in[15:0] multiplexer output is to tim_ti1 input
B_0x0 = 0x0,
/// The tim_ti1_in[15:0], tim_ti2_in[15:0] and tim_ti3_in[15:0] multiplexers outputs are XORed and connected to the tim_ti1 input.
B_0x1 = 0x1,
} = .B_0x0,
reserved25: u17 = 0,
/// MMS[3]
MMS_1: u1 = 0x0,
padding: u6 = 0,
}),
/// TIM2 slave mode control register
/// offset: 0x08
TIM2_SMCR: mmio.Mmio(packed struct(u32) {
/// SMS[0]: Slave mode selection
SMS: enum(u3) {
/// Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock.
B_0x0 = 0x0,
/// Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level.
B_0x1 = 0x1,
/// Encoder mode 2 - Counter counts up/down on tim_ti2fp2 edge depending on tim_ti1fp1 level.
B_0x2 = 0x2,
/// Encoder mode 3 - Counter counts up/down on both tim_ti1fp1 and tim_ti2fp2 edges depending on the level of the other input.
B_0x3 = 0x3,
/// Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers.
B_0x4 = 0x4,
/// Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high.
B_0x5 = 0x5,
/// Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset).
B_0x6 = 0x6,
/// External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter.
B_0x7 = 0x7,
} = .B_0x0,
/// OCREF clear selection
OCCS: enum(u1) {
/// tim_ocref_clr_int is connected to the tim_ocref_clr input
B_0x0 = 0x0,
/// tim_ocref_clr_int is connected to tim_etrf
B_0x1 = 0x1,
} = .B_0x0,
/// TS[0]: Trigger selection
TS: enum(u3) {
/// Internal trigger 0 (tim_itr0)
B_0x0 = 0x0,
/// Internal trigger 1 (tim_itr1)
B_0x1 = 0x1,
/// Internal trigger 2 (tim_itr2)
B_0x2 = 0x2,
/// Internal trigger 3 (tim_itr3)
B_0x3 = 0x3,
/// tim_ti1 edge detector (tim_ti1f_ed)
B_0x4 = 0x4,
/// Filtered timer input 1 (tim_ti1fp1)
B_0x5 = 0x5,
/// Filtered timer input 2 (tim_ti2fp2)
B_0x6 = 0x6,
/// External trigger input (tim_etrf)
B_0x7 = 0x7,
} = .B_0x0,
/// Master/Slave mode
MSM: enum(u1) {
/// No action
B_0x0 = 0x0,
/// The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo).
B_0x1 = 0x1,
} = .B_0x0,
/// External trigger filter
ETF: enum(u4) {
/// No filter, sampling is done at fless thansub>DTSless than/sub>
B_0x0 = 0x0,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2
B_0x1 = 0x1,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4
B_0x2 = 0x2,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8
B_0x3 = 0x3,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6
B_0x4 = 0x4,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8
B_0x5 = 0x5,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6
B_0x6 = 0x6,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8
B_0x7 = 0x7,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6
B_0x8 = 0x8,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8
B_0x9 = 0x9,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5
B_0xA = 0xa,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6
B_0xB = 0xb,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8
B_0xC = 0xc,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5
B_0xD = 0xd,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6
B_0xE = 0xe,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8
B_0xF = 0xf,
} = .B_0x0,
/// External trigger prescaler
ETPS: enum(u2) {
/// Prescaler OFF
B_0x0 = 0x0,
/// tim_etrp frequency divided by 2
B_0x1 = 0x1,
/// tim_etrp frequency divided by 4
B_0x2 = 0x2,
/// tim_etrp frequency divided by 8
B_0x3 = 0x3,
} = .B_0x0,
/// External clock enable
ECE: enum(u1) {
/// External clock mode 2 disabled
B_0x0 = 0x0,
/// External clock mode 2 enabled.
B_0x1 = 0x1,
} = .B_0x0,
/// External trigger polarity
ETP: enum(u1) {
/// tim_etr_in is non-inverted, active at high level or rising edge
B_0x0 = 0x0,
/// tim_etr_in is inverted, active at low level or falling edge
B_0x1 = 0x1,
} = .B_0x0,
/// SMS[3]
SMS_1: u1 = 0x0,
reserved20: u3 = 0,
/// TS[4:3]
TS_1: u2 = 0x0,
reserved24: u2 = 0,
/// SMS preload enable
SMSPE: enum(u1) {
/// SMS[3:0] bitfield is not preloaded
B_0x0 = 0x0,
/// SMS[3:0] preload is enabled
B_0x1 = 0x1,
} = .B_0x0,
/// SMS preload source
SMSPS: enum(u1) {
/// The transfer is triggered by the Timer's Update event
B_0x0 = 0x0,
/// The transfer is triggered by the Index event
B_0x1 = 0x1,
} = .B_0x0,
padding: u6 = 0,
}),
/// TIM2 DMA/Interrupt enable register
/// offset: 0x0c
TIM2_DIER: mmio.Mmio(packed struct(u32) {
/// Update interrupt enable
UIE: enum(u1) {
/// Update interrupt disabled.
B_0x0 = 0x0,
/// Update interrupt enabled.
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/Compare 1 interrupt enable
CC1IE: enum(u1) {
/// CC1 interrupt disabled.
B_0x0 = 0x0,
/// CC1 interrupt enabled.
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/Compare 2 interrupt enable
CC2IE: enum(u1) {
/// CC2 interrupt disabled.
B_0x0 = 0x0,
/// CC2 interrupt enabled.
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/Compare 3 interrupt enable
CC3IE: enum(u1) {
/// CC3 interrupt disabled.
B_0x0 = 0x0,
/// CC3 interrupt enabled.
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/Compare 4 interrupt enable
CC4IE: enum(u1) {
/// CC4 interrupt disabled.
B_0x0 = 0x0,
/// CC4 interrupt enabled.
B_0x1 = 0x1,
} = .B_0x0,
reserved6: u1 = 0,
/// Trigger interrupt enable
TIE: enum(u1) {
/// Trigger interrupt disabled.
B_0x0 = 0x0,
/// Trigger interrupt enabled.
B_0x1 = 0x1,
} = .B_0x0,
reserved8: u1 = 0,
/// Update DMA request enable
UDE: enum(u1) {
/// Update DMA request disabled.
B_0x0 = 0x0,
/// Update DMA request enabled.
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/Compare 1 DMA request enable
CC1DE: enum(u1) {
/// CC1 DMA request disabled.
B_0x0 = 0x0,
/// CC1 DMA request enabled.
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/Compare 2 DMA request enable
CC2DE: enum(u1) {
/// CC2 DMA request disabled.
B_0x0 = 0x0,
/// CC2 DMA request enabled.
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/Compare 3 DMA request enable
CC3DE: enum(u1) {
/// CC3 DMA request disabled.
B_0x0 = 0x0,
/// CC3 DMA request enabled.
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/Compare 4 DMA request enable
CC4DE: enum(u1) {
/// CC4 DMA request disabled.
B_0x0 = 0x0,
/// CC4 DMA request enabled.
B_0x1 = 0x1,
} = .B_0x0,
reserved14: u1 = 0,
/// Trigger DMA request enable
TDE: enum(u1) {
/// Trigger DMA request disabled.
B_0x0 = 0x0,
/// Trigger DMA request enabled.
B_0x1 = 0x1,
} = .B_0x0,
reserved20: u5 = 0,
/// Index interrupt enable
IDXIE: enum(u1) {
/// Index interrupt disabled
B_0x0 = 0x0,
/// Index interrupt enabled
B_0x1 = 0x1,
} = .B_0x0,
/// Direction change interrupt enable
DIRIE: enum(u1) {
/// Direction change interrupt disabled
B_0x0 = 0x0,
/// Direction change interrupt enabled
B_0x1 = 0x1,
} = .B_0x0,
/// Index error interrupt enable
IERRIE: enum(u1) {
/// Index error interrupt disabled
B_0x0 = 0x0,
/// Index error interrupt enabled
B_0x1 = 0x1,
} = .B_0x0,
/// Transition error interrupt enable
TERRIE: enum(u1) {
/// Transition error interrupt disabled
B_0x0 = 0x0,
/// Transition error interrupt enabled
B_0x1 = 0x1,
} = .B_0x0,
padding: u8 = 0,
}),
/// TIM2 status register
/// offset: 0x10
TIM2_SR: mmio.Mmio(packed struct(u32) {
/// Update interrupt flag
UIF: enum(u1) {
/// No update occurred
B_0x0 = 0x0,
/// Update interrupt pending.
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/compare 1 interrupt flag
CC1IF: enum(u1) {
/// No compare match / No input capture occurred
B_0x0 = 0x0,
/// A compare match or an input capture occurred
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/Compare 2 interrupt flag
CC2IF: u1 = 0x0,
/// Capture/Compare 3 interrupt flag
CC3IF: u1 = 0x0,
/// Capture/Compare 4 interrupt flag
CC4IF: u1 = 0x0,
reserved6: u1 = 0,
/// Trigger interrupt flag
TIF: enum(u1) {
/// No trigger event occurred.
B_0x0 = 0x0,
/// Trigger interrupt pending.
B_0x1 = 0x1,
} = .B_0x0,
reserved9: u2 = 0,
/// Capture/Compare 1 overcapture flag
CC1OF: enum(u1) {
/// No overcapture has been detected.
B_0x0 = 0x0,
/// The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/compare 2 overcapture flag
CC2OF: u1 = 0x0,
/// Capture/Compare 3 overcapture flag
CC3OF: u1 = 0x0,
/// Capture/Compare 4 overcapture flag
CC4OF: u1 = 0x0,
reserved20: u7 = 0,
/// Index interrupt flag
IDXF: enum(u1) {
/// No index event occurred.
B_0x0 = 0x0,
/// An index event has occurred
B_0x1 = 0x1,
} = .B_0x0,
/// Direction change interrupt flag
DIRF: enum(u1) {
/// No direction change
B_0x0 = 0x0,
/// Direction change
B_0x1 = 0x1,
} = .B_0x0,
/// Index error interrupt flag
IERRF: enum(u1) {
/// No index error has been detected.
B_0x0 = 0x0,
/// An index error has been detected
B_0x1 = 0x1,
} = .B_0x0,
/// Transition error interrupt flag
TERRF: enum(u1) {
/// No encoder transition error has been detected.
B_0x0 = 0x0,
/// An encoder transition error has been detected
B_0x1 = 0x1,
} = .B_0x0,
padding: u8 = 0,
}),
/// TIM2 event generation register
/// offset: 0x14
TIM2_EGR: mmio.Mmio(packed struct(u16) {
/// Update generation
UG: enum(u1) {
/// No action
B_0x0 = 0x0,
/// Re-initialize the counter and generates an update of the registers.
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/compare 1 generation
CC1G: enum(u1) {
/// No action
B_0x0 = 0x0,
/// A capture/compare event is generated on channel 1:
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/compare 2 generation
CC2G: u1 = 0x0,
/// Capture/compare 3 generation
CC3G: u1 = 0x0,
/// Capture/compare 4 generation
CC4G: u1 = 0x0,
reserved6: u1 = 0,
/// Trigger generation
TG: enum(u1) {
/// No action
B_0x0 = 0x0,
/// The TIF flag is set in TIMx_SR register.
B_0x1 = 0x1,
} = .B_0x0,
padding: u9 = 0,
}),
/// offset: 0x16
reserved22: [2]u8,
/// TIM2 capture/compare mode register 1 [alternate]
/// offset: 0x18
TIM2_CCMR1: mmio.Mmio(packed struct(u32) {
/// Capture/Compare 1 selection
CC1S: enum(u2) {
/// CC1 channel is configured as output
B_0x0 = 0x0,
/// CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1
B_0x1 = 0x1,
/// CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2
B_0x2 = 0x2,
/// CC1 channel is configured as input, tim_ic1 is mapped on tim_trc.
B_0x3 = 0x3,
} = .B_0x0,
/// Input capture 1 prescaler
IC1PSC: enum(u2) {
/// no prescaler, capture is done each time an edge is detected on the capture input
B_0x0 = 0x0,
/// capture is done once every 2 events
B_0x1 = 0x1,
/// capture is done once every 4 events
B_0x2 = 0x2,
/// capture is done once every 8 events
B_0x3 = 0x3,
} = .B_0x0,
/// Input capture 1 filter
IC1F: enum(u4) {
/// No filter, sampling is done at fless thansub>DTSless than/sub>
B_0x0 = 0x0,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2
B_0x1 = 0x1,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4
B_0x2 = 0x2,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8
B_0x3 = 0x3,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6
B_0x4 = 0x4,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8
B_0x5 = 0x5,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6
B_0x6 = 0x6,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8
B_0x7 = 0x7,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6
B_0x8 = 0x8,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8
B_0x9 = 0x9,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5
B_0xA = 0xa,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6
B_0xB = 0xb,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8
B_0xC = 0xc,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5
B_0xD = 0xd,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6
B_0xE = 0xe,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8
B_0xF = 0xf,
} = .B_0x0,
/// Capture/compare 2 selection
CC2S: enum(u2) {
/// CC2 channel is configured as output.
B_0x0 = 0x0,
/// CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2.
B_0x1 = 0x1,
/// CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1.
B_0x2 = 0x2,
/// CC2 channel is configured as input, tim_ic2 is mapped on tim_trc.
B_0x3 = 0x3,
} = .B_0x0,
/// Input capture 2 prescaler
IC2PSC: u2 = 0x0,
/// Input capture 2 filter
IC2F: u4 = 0x0,
padding: u16 = 0,
}),
/// TIM2 capture/compare mode register 2 [alternate]
/// offset: 0x1c
TIM2_CCMR2: mmio.Mmio(packed struct(u32) {
/// Capture/Compare 3 selection
CC3S: enum(u2) {
/// CC3 channel is configured as output
B_0x0 = 0x0,
/// CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3
B_0x1 = 0x1,
/// CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4
B_0x2 = 0x2,
/// CC3 channel is configured as input, tim_ic3 is mapped on tim_trc.
B_0x3 = 0x3,
} = .B_0x0,
/// Input capture 3 prescaler
IC3PSC: u2 = 0x0,
/// Input capture 3 filter
IC3F: u4 = 0x0,
/// Capture/Compare 4 selection
CC4S: enum(u2) {
/// CC4 channel is configured as output
B_0x0 = 0x0,
/// CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4
B_0x1 = 0x1,
/// CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3
B_0x2 = 0x2,
/// CC4 channel is configured as input, tim_ic4 is mapped on tim_trc.
B_0x3 = 0x3,
} = .B_0x0,
/// Input capture 4 prescaler
IC4PSC: u2 = 0x0,
/// Input capture 4 filter
IC4F: u4 = 0x0,
padding: u16 = 0,
}),
/// TIM2 capture/compare enable register
/// offset: 0x20
TIM2_CCER: mmio.Mmio(packed struct(u16) {
/// Capture/Compare 1 output enable.
CC1E: enum(u1) {
/// Capture mode disabled / OC1 is not active
B_0x0 = 0x0,
/// Capture mode enabled / OC1 signal is output on the corresponding output pin
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/Compare 1 output Polarity.
CC1P: enum(u1) {
/// OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)
B_0x0 = 0x0,
/// OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)
B_0x1 = 0x1,
} = .B_0x0,
reserved3: u1 = 0,
/// Capture/Compare 1 output Polarity.
CC1NP: u1 = 0x0,
/// Capture/Compare 2 output enable.
CC2E: u1 = 0x0,
/// Capture/Compare 2 output Polarity.
CC2P: u1 = 0x0,
reserved7: u1 = 0,
/// Capture/Compare 2 output Polarity.
CC2NP: u1 = 0x0,
/// Capture/Compare 3 output enable.
CC3E: u1 = 0x0,
/// Capture/Compare 3 output Polarity.
CC3P: u1 = 0x0,
reserved11: u1 = 0,
/// Capture/Compare 3 output Polarity.
CC3NP: u1 = 0x0,
/// Capture/Compare 4 output enable.
CC4E: u1 = 0x0,
/// Capture/Compare 4 output Polarity.
CC4P: u1 = 0x0,
reserved15: u1 = 0,
/// Capture/Compare 4 output Polarity.
CC4NP: u1 = 0x0,
}),
/// offset: 0x22
reserved34: [2]u8,
/// TIM2 counter
/// offset: 0x24
TIM2_CNT: mmio.Mmio(packed struct(u32) {
/// Least significant part of counter value
CNT: u31 = 0x0,
/// Value depends on IUFREMAP in TIMx_CR1.
UIFCPY_CNT: u1 = 0x0,
}),
/// TIM2 prescaler
/// offset: 0x28
TIM2_PSC: mmio.Mmio(packed struct(u16) {
/// Prescaler value
PSC: u16 = 0x0,
}),
/// offset: 0x2a
reserved42: [2]u8,
/// TIM2 auto-reload register
/// offset: 0x2c
TIM2_ARR: mmio.Mmio(packed struct(u32) {
/// Auto-reload value
ARR: u32 = 0xFFFFFFFF,
}),
/// offset: 0x30
reserved48: [4]u8,
/// TIM2 capture/compare register 1
/// offset: 0x34
TIM2_CCR1: mmio.Mmio(packed struct(u32) {
/// Capture/compare 1 value
CCR1: u32 = 0x0,
}),
/// TIM2 capture/compare register 2
/// offset: 0x38
TIM2_CCR2: mmio.Mmio(packed struct(u32) {
/// Capture/compare 2 value
CCR2: u32 = 0x0,
}),
/// TIM2 capture/compare register 3
/// offset: 0x3c
TIM2_CCR3: mmio.Mmio(packed struct(u32) {
/// Capture/compare 3 value
CCR3: u32 = 0x0,
}),
/// TIM2 capture/compare register 4
/// offset: 0x40
TIM2_CCR4: mmio.Mmio(packed struct(u32) {
/// Capture/compare 4 value
CCR4: u32 = 0x0,
}),
/// offset: 0x44
reserved68: [20]u8,
/// TIM2 timer encoder control register
/// offset: 0x58
TIM2_ECR: mmio.Mmio(packed struct(u32) {
/// Index enable
IE: enum(u1) {
/// Index disabled
B_0x0 = 0x0,
/// Index enabled
B_0x1 = 0x1,
} = .B_0x0,
/// Index direction
IDIR: enum(u2) {
/// Index resets the counter whatever the direction
B_0x0 = 0x0,
/// Index resets the counter when up-counting only
B_0x1 = 0x1,
/// Index resets the counter when down-counting only
B_0x2 = 0x2,
_,
} = .B_0x0,
reserved5: u2 = 0,
/// First index
FIDX: enum(u1) {
/// Index is always active
B_0x0 = 0x0,
/// the first Index only resets the counter
B_0x1 = 0x1,
} = .B_0x0,
/// Index positioning
IPOS: enum(u2) {
/// Index resets the counter when AB = 00
B_0x0 = 0x0,
/// Index resets the counter when AB = 01
B_0x1 = 0x1,
/// Index resets the counter when AB = 10
B_0x2 = 0x2,
/// Index resets the counter when AB = 11
B_0x3 = 0x3,
} = .B_0x0,
reserved16: u8 = 0,
/// Pulse width
PW: u8 = 0x0,
/// Pulse width prescaler
PWPRSC: u3 = 0x0,
padding: u5 = 0,
}),
/// TIM2 timer input selection register
/// offset: 0x5c
TIM2_TISEL: mmio.Mmio(packed struct(u32) {
/// Selects tim_ti1[15:0] input
TI1SEL: enum(u4) {
/// tim_ti1_in0: TIMx_CH1
B_0x0 = 0x0,
/// tim_ti1_in1
B_0x1 = 0x1,
/// tim_ti1_in15
B_0xF = 0xf,
_,
} = .B_0x0,
reserved8: u4 = 0,
/// Selects tim_ti2[15:0] input
TI2SEL: enum(u4) {
/// tim_ti2_in0: TIMx_CH2
B_0x0 = 0x0,
/// tim_ti2_in1
B_0x1 = 0x1,
/// tim_ti2_in15
B_0xF = 0xf,
_,
} = .B_0x0,
reserved16: u4 = 0,
/// Selects tim_ti3[15:0] input
TI3SEL: enum(u4) {
/// tim_ti3_in0: TIMx_CH3
B_0x0 = 0x0,
/// tim_ti3_in1
B_0x1 = 0x1,
/// tim_ti3_in15
B_0xF = 0xf,
_,
} = .B_0x0,
reserved24: u4 = 0,
/// Selects tim_ti4[15:0] input
TI4SEL: enum(u4) {
/// tim_ti4_in0: TIMx_CH4
B_0x0 = 0x0,
/// tim_ti4_in1
B_0x1 = 0x1,
/// tim_ti4_in15
B_0xF = 0xf,
_,
} = .B_0x0,
padding: u4 = 0,
}),
/// TIM2 alternate function register 1
/// offset: 0x60
TIM2_AF1: mmio.Mmio(packed struct(u32) {
reserved14: u14 = 0,
/// etr_in source selection
ETRSEL: enum(u4) {
/// tim_etr0: TIMx_ETR input
B_0x0 = 0x0,
/// tim_etr1
B_0x1 = 0x1,
/// tim_etr15
B_0xF = 0xf,
_,
} = .B_0x0,
padding: u14 = 0,
}),
/// TIM2 alternate function register 2
/// offset: 0x64
TIM2_AF2: mmio.Mmio(packed struct(u32) {
reserved16: u16 = 0,
/// ocref_clr source selection
OCRSEL: enum(u3) {
/// tim_ocref_clr0
B_0x0 = 0x0,
/// tim_ocref_clr1
B_0x1 = 0x1,
/// tim_ocref_clr7
B_0x7 = 0x7,
_,
} = .B_0x0,
padding: u13 = 0,
}),
/// offset: 0x68
reserved104: [884]u8,
/// TIM2 DMA control register
/// offset: 0x3dc
TIM2_DCR: mmio.Mmio(packed struct(u32) {
/// DMA base address
DBA: enum(u5) {
/// TIMx_CR1,
B_0x0 = 0x0,
/// TIMx_CR2,
B_0x1 = 0x1,
/// TIMx_SMCR,
B_0x2 = 0x2,
_,
} = .B_0x0,
reserved8: u3 = 0,
/// DMA burst length
DBL: enum(u5) {
/// 1 transfer
B_0x0 = 0x0,
/// 2 transfers
B_0x1 = 0x1,
/// 3 transfers
B_0x2 = 0x2,
/// 26 transfers
B_0x1A = 0x1a,
_,
} = .B_0x0,
padding: u19 = 0,
}),
/// TIM2 DMA address for full transfer
/// offset: 0x3e0
TIM2_DMAR: mmio.Mmio(packed struct(u32) {
/// DMA register for burst accesses
DMAB: u32 = 0x0,
}),
};

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src/stm32g4/types/peripherals/TIM3.zig Normal file
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const microzig = @import("microzig");
const mmio = microzig.mmio;
const types = @import("../../types.zig");
/// Advanced-timers
pub const TIM3 = extern struct {
/// TIM3 control register 1
/// offset: 0x00
TIM3_CR1: mmio.Mmio(packed struct(u16) {
/// Counter enable
CEN: enum(u1) {
/// Counter disabled
B_0x0 = 0x0,
/// Counter enabled
B_0x1 = 0x1,
} = .B_0x0,
/// Update disable
UDIS: enum(u1) {
/// UEV enabled.
B_0x0 = 0x0,
/// UEV disabled.
B_0x1 = 0x1,
} = .B_0x0,
/// Update request source
URS: enum(u1) {
/// Any of the following events generate an update interrupt or DMA request if enabled.
B_0x0 = 0x0,
/// Only counter overflow/underflow generates an update interrupt or DMA request if enabled.
B_0x1 = 0x1,
} = .B_0x0,
/// One-pulse mode
OPM: enum(u1) {
/// Counter is not stopped at update event
B_0x0 = 0x0,
/// Counter stops counting at the next update event (clearing the bit CEN)
B_0x1 = 0x1,
} = .B_0x0,
/// Direction
DIR: enum(u1) {
/// Counter used as upcounter
B_0x0 = 0x0,
/// Counter used as downcounter
B_0x1 = 0x1,
} = .B_0x0,
/// Center-aligned mode selection
CMS: enum(u2) {
/// Edge-aligned mode.
B_0x0 = 0x0,
/// Center-aligned mode 1.
B_0x1 = 0x1,
/// Center-aligned mode 2.
B_0x2 = 0x2,
/// Center-aligned mode 3.
B_0x3 = 0x3,
} = .B_0x0,
/// Auto-reload preload enable
ARPE: enum(u1) {
/// TIMx_ARR register is not buffered
B_0x0 = 0x0,
/// TIMx_ARR register is buffered
B_0x1 = 0x1,
} = .B_0x0,
/// Clock division
CKD: enum(u2) {
/// tless thansub>DTSless than/sub> = tless thansub>tim_ker_ckless than/sub>
B_0x0 = 0x0,
/// tless thansub>DTSless than/sub> = 2 tless thansub>tim_ker_ckless than/sub>
B_0x1 = 0x1,
/// tless thansub>DTSless than/sub> = 4 tless thansub>tim_ker_ckless than/sub>
B_0x2 = 0x2,
_,
} = .B_0x0,
reserved11: u1 = 0,
/// UIF status bit remapping
UIFREMAP: enum(u1) {
/// No remapping.
B_0x0 = 0x0,
/// Remapping enabled.
B_0x1 = 0x1,
} = .B_0x0,
/// Dithering Enable
DITHEN: enum(u1) {
/// Dithering disabled
B_0x0 = 0x0,
/// Dithering enabled
B_0x1 = 0x1,
} = .B_0x0,
padding: u3 = 0,
}),
/// offset: 0x02
reserved2: [2]u8,
/// TIM3 control register 2
/// offset: 0x04
TIM3_CR2: mmio.Mmio(packed struct(u32) {
reserved3: u3 = 0,
/// Capture/compare DMA selection
CCDS: enum(u1) {
/// CCx DMA request sent when CCx event occurs
B_0x0 = 0x0,
/// CCx DMA requests sent when update event occurs
B_0x1 = 0x1,
} = .B_0x0,
/// MMS[0]: Master mode selection
MMS: enum(u3) {
/// Reset - the UG bit from the TIMx_EGR register is used as trigger output (tim_trgo).
B_0x0 = 0x0,
/// Enable - the Counter enable signal, CNT_EN, is used as trigger output (tim_trgo).
B_0x1 = 0x1,
/// Update - The update event is selected as trigger output (tim_trgo).
B_0x2 = 0x2,
/// Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred (tim_trgo).
B_0x3 = 0x3,
/// Compare - tim_oc1refc signal is used as trigger output (tim_trgo)
B_0x4 = 0x4,
/// Compare - tim_oc2refc signal is used as trigger output (tim_trgo)
B_0x5 = 0x5,
/// Compare - tim_oc3refc signal is used as trigger output (tim_trgo)
B_0x6 = 0x6,
/// Compare - tim_oc4refc signal is used as trigger output (tim_trgo)
B_0x7 = 0x7,
} = .B_0x0,
/// tim_ti1 selection
TI1S: enum(u1) {
/// The tim_ti1_in[15:0] multiplexer output is to tim_ti1 input
B_0x0 = 0x0,
/// The tim_ti1_in[15:0], tim_ti2_in[15:0] and tim_ti3_in[15:0] multiplexers outputs are XORed and connected to the tim_ti1 input.
B_0x1 = 0x1,
} = .B_0x0,
reserved25: u17 = 0,
/// MMS[3]
MMS_1: u1 = 0x0,
padding: u6 = 0,
}),
/// TIM3 slave mode control register
/// offset: 0x08
TIM3_SMCR: mmio.Mmio(packed struct(u32) {
/// SMS[0]: Slave mode selection
SMS: enum(u3) {
/// Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock.
B_0x0 = 0x0,
/// Encoder mode 1 - Counter counts up/down on tim_ti1fp1 edge depending on tim_ti2fp2 level.
B_0x1 = 0x1,
/// Encoder mode 2 - Counter counts up/down on tim_ti2fp2 edge depending on tim_ti1fp1 level.
B_0x2 = 0x2,
/// Encoder mode 3 - Counter counts up/down on both tim_ti1fp1 and tim_ti2fp2 edges depending on the level of the other input.
B_0x3 = 0x3,
/// Reset Mode - Rising edge of the selected trigger input (tim_trgi) reinitializes the counter and generates an update of the registers.
B_0x4 = 0x4,
/// Gated Mode - The counter clock is enabled when the trigger input (tim_trgi) is high.
B_0x5 = 0x5,
/// Trigger Mode - The counter starts at a rising edge of the trigger tim_trgi (but it is not reset).
B_0x6 = 0x6,
/// External Clock Mode 1 - Rising edges of the selected trigger (tim_trgi) clock the counter.
B_0x7 = 0x7,
} = .B_0x0,
/// OCREF clear selection
OCCS: enum(u1) {
/// tim_ocref_clr_int is connected to the tim_ocref_clr input
B_0x0 = 0x0,
/// tim_ocref_clr_int is connected to tim_etrf
B_0x1 = 0x1,
} = .B_0x0,
/// TS[0]: Trigger selection
TS: enum(u3) {
/// Internal trigger 0 (tim_itr0)
B_0x0 = 0x0,
/// Internal trigger 1 (tim_itr1)
B_0x1 = 0x1,
/// Internal trigger 2 (tim_itr2)
B_0x2 = 0x2,
/// Internal trigger 3 (tim_itr3)
B_0x3 = 0x3,
/// tim_ti1 edge detector (tim_ti1f_ed)
B_0x4 = 0x4,
/// Filtered timer input 1 (tim_ti1fp1)
B_0x5 = 0x5,
/// Filtered timer input 2 (tim_ti2fp2)
B_0x6 = 0x6,
/// External trigger input (tim_etrf)
B_0x7 = 0x7,
} = .B_0x0,
/// Master/Slave mode
MSM: enum(u1) {
/// No action
B_0x0 = 0x0,
/// The effect of an event on the trigger input (tim_trgi) is delayed to allow a perfect synchronization between the current timer and its slaves (through tim_trgo).
B_0x1 = 0x1,
} = .B_0x0,
/// External trigger filter
ETF: enum(u4) {
/// No filter, sampling is done at fless thansub>DTSless than/sub>
B_0x0 = 0x0,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2
B_0x1 = 0x1,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4
B_0x2 = 0x2,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8
B_0x3 = 0x3,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6
B_0x4 = 0x4,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8
B_0x5 = 0x5,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6
B_0x6 = 0x6,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8
B_0x7 = 0x7,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6
B_0x8 = 0x8,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8
B_0x9 = 0x9,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5
B_0xA = 0xa,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6
B_0xB = 0xb,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8
B_0xC = 0xc,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5
B_0xD = 0xd,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6
B_0xE = 0xe,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8
B_0xF = 0xf,
} = .B_0x0,
/// External trigger prescaler
ETPS: enum(u2) {
/// Prescaler OFF
B_0x0 = 0x0,
/// tim_etrp frequency divided by 2
B_0x1 = 0x1,
/// tim_etrp frequency divided by 4
B_0x2 = 0x2,
/// tim_etrp frequency divided by 8
B_0x3 = 0x3,
} = .B_0x0,
/// External clock enable
ECE: enum(u1) {
/// External clock mode 2 disabled
B_0x0 = 0x0,
/// External clock mode 2 enabled.
B_0x1 = 0x1,
} = .B_0x0,
/// External trigger polarity
ETP: enum(u1) {
/// tim_etr_in is non-inverted, active at high level or rising edge
B_0x0 = 0x0,
/// tim_etr_in is inverted, active at low level or falling edge
B_0x1 = 0x1,
} = .B_0x0,
/// SMS[3]
SMS_1: u1 = 0x0,
reserved20: u3 = 0,
/// TS[4:3]
TS_1: u2 = 0x0,
reserved24: u2 = 0,
/// SMS preload enable
SMSPE: enum(u1) {
/// SMS[3:0] bitfield is not preloaded
B_0x0 = 0x0,
/// SMS[3:0] preload is enabled
B_0x1 = 0x1,
} = .B_0x0,
/// SMS preload source
SMSPS: enum(u1) {
/// The transfer is triggered by the Timer's Update event
B_0x0 = 0x0,
/// The transfer is triggered by the Index event
B_0x1 = 0x1,
} = .B_0x0,
padding: u6 = 0,
}),
/// TIM3 DMA/Interrupt enable register
/// offset: 0x0c
TIM3_DIER: mmio.Mmio(packed struct(u32) {
/// Update interrupt enable
UIE: enum(u1) {
/// Update interrupt disabled.
B_0x0 = 0x0,
/// Update interrupt enabled.
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/Compare 1 interrupt enable
CC1IE: enum(u1) {
/// CC1 interrupt disabled.
B_0x0 = 0x0,
/// CC1 interrupt enabled.
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/Compare 2 interrupt enable
CC2IE: enum(u1) {
/// CC2 interrupt disabled.
B_0x0 = 0x0,
/// CC2 interrupt enabled.
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/Compare 3 interrupt enable
CC3IE: enum(u1) {
/// CC3 interrupt disabled.
B_0x0 = 0x0,
/// CC3 interrupt enabled.
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/Compare 4 interrupt enable
CC4IE: enum(u1) {
/// CC4 interrupt disabled.
B_0x0 = 0x0,
/// CC4 interrupt enabled.
B_0x1 = 0x1,
} = .B_0x0,
reserved6: u1 = 0,
/// Trigger interrupt enable
TIE: enum(u1) {
/// Trigger interrupt disabled.
B_0x0 = 0x0,
/// Trigger interrupt enabled.
B_0x1 = 0x1,
} = .B_0x0,
reserved8: u1 = 0,
/// Update DMA request enable
UDE: enum(u1) {
/// Update DMA request disabled.
B_0x0 = 0x0,
/// Update DMA request enabled.
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/Compare 1 DMA request enable
CC1DE: enum(u1) {
/// CC1 DMA request disabled.
B_0x0 = 0x0,
/// CC1 DMA request enabled.
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/Compare 2 DMA request enable
CC2DE: enum(u1) {
/// CC2 DMA request disabled.
B_0x0 = 0x0,
/// CC2 DMA request enabled.
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/Compare 3 DMA request enable
CC3DE: enum(u1) {
/// CC3 DMA request disabled.
B_0x0 = 0x0,
/// CC3 DMA request enabled.
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/Compare 4 DMA request enable
CC4DE: enum(u1) {
/// CC4 DMA request disabled.
B_0x0 = 0x0,
/// CC4 DMA request enabled.
B_0x1 = 0x1,
} = .B_0x0,
reserved14: u1 = 0,
/// Trigger DMA request enable
TDE: enum(u1) {
/// Trigger DMA request disabled.
B_0x0 = 0x0,
/// Trigger DMA request enabled.
B_0x1 = 0x1,
} = .B_0x0,
reserved20: u5 = 0,
/// Index interrupt enable
IDXIE: enum(u1) {
/// Index interrupt disabled
B_0x0 = 0x0,
/// Index interrupt enabled
B_0x1 = 0x1,
} = .B_0x0,
/// Direction change interrupt enable
DIRIE: enum(u1) {
/// Direction change interrupt disabled
B_0x0 = 0x0,
/// Direction change interrupt enabled
B_0x1 = 0x1,
} = .B_0x0,
/// Index error interrupt enable
IERRIE: enum(u1) {
/// Index error interrupt disabled
B_0x0 = 0x0,
/// Index error interrupt enabled
B_0x1 = 0x1,
} = .B_0x0,
/// Transition error interrupt enable
TERRIE: enum(u1) {
/// Transition error interrupt disabled
B_0x0 = 0x0,
/// Transition error interrupt enabled
B_0x1 = 0x1,
} = .B_0x0,
padding: u8 = 0,
}),
/// TIM3 status register
/// offset: 0x10
TIM3_SR: mmio.Mmio(packed struct(u32) {
/// Update interrupt flag
UIF: enum(u1) {
/// No update occurred
B_0x0 = 0x0,
/// Update interrupt pending.
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/compare 1 interrupt flag
CC1IF: enum(u1) {
/// No compare match / No input capture occurred
B_0x0 = 0x0,
/// A compare match or an input capture occurred
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/Compare 2 interrupt flag
CC2IF: u1 = 0x0,
/// Capture/Compare 3 interrupt flag
CC3IF: u1 = 0x0,
/// Capture/Compare 4 interrupt flag
CC4IF: u1 = 0x0,
reserved6: u1 = 0,
/// Trigger interrupt flag
TIF: enum(u1) {
/// No trigger event occurred.
B_0x0 = 0x0,
/// Trigger interrupt pending.
B_0x1 = 0x1,
} = .B_0x0,
reserved9: u2 = 0,
/// Capture/Compare 1 overcapture flag
CC1OF: enum(u1) {
/// No overcapture has been detected.
B_0x0 = 0x0,
/// The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/compare 2 overcapture flag
CC2OF: u1 = 0x0,
/// Capture/Compare 3 overcapture flag
CC3OF: u1 = 0x0,
/// Capture/Compare 4 overcapture flag
CC4OF: u1 = 0x0,
reserved20: u7 = 0,
/// Index interrupt flag
IDXF: enum(u1) {
/// No index event occurred.
B_0x0 = 0x0,
/// An index event has occurred
B_0x1 = 0x1,
} = .B_0x0,
/// Direction change interrupt flag
DIRF: enum(u1) {
/// No direction change
B_0x0 = 0x0,
/// Direction change
B_0x1 = 0x1,
} = .B_0x0,
/// Index error interrupt flag
IERRF: enum(u1) {
/// No index error has been detected.
B_0x0 = 0x0,
/// An index error has been detected
B_0x1 = 0x1,
} = .B_0x0,
/// Transition error interrupt flag
TERRF: enum(u1) {
/// No encoder transition error has been detected.
B_0x0 = 0x0,
/// An encoder transition error has been detected
B_0x1 = 0x1,
} = .B_0x0,
padding: u8 = 0,
}),
/// TIM3 event generation register
/// offset: 0x14
TIM3_EGR: mmio.Mmio(packed struct(u16) {
/// Update generation
UG: enum(u1) {
/// No action
B_0x0 = 0x0,
/// Re-initialize the counter and generates an update of the registers.
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/compare 1 generation
CC1G: enum(u1) {
/// No action
B_0x0 = 0x0,
/// A capture/compare event is generated on channel 1:
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/compare 2 generation
CC2G: u1 = 0x0,
/// Capture/compare 3 generation
CC3G: u1 = 0x0,
/// Capture/compare 4 generation
CC4G: u1 = 0x0,
reserved6: u1 = 0,
/// Trigger generation
TG: enum(u1) {
/// No action
B_0x0 = 0x0,
/// The TIF flag is set in TIMx_SR register.
B_0x1 = 0x1,
} = .B_0x0,
padding: u9 = 0,
}),
/// offset: 0x16
reserved22: [2]u8,
/// TIM3 capture/compare mode register 1 [alternate]
/// offset: 0x18
TIM3_CCMR1: mmio.Mmio(packed struct(u32) {
/// Capture/Compare 1 selection
CC1S: enum(u2) {
/// CC1 channel is configured as output
B_0x0 = 0x0,
/// CC1 channel is configured as input, tim_ic1 is mapped on tim_ti1
B_0x1 = 0x1,
/// CC1 channel is configured as input, tim_ic1 is mapped on tim_ti2
B_0x2 = 0x2,
/// CC1 channel is configured as input, tim_ic1 is mapped on tim_trc.
B_0x3 = 0x3,
} = .B_0x0,
/// Input capture 1 prescaler
IC1PSC: enum(u2) {
/// no prescaler, capture is done each time an edge is detected on the capture input
B_0x0 = 0x0,
/// capture is done once every 2 events
B_0x1 = 0x1,
/// capture is done once every 4 events
B_0x2 = 0x2,
/// capture is done once every 8 events
B_0x3 = 0x3,
} = .B_0x0,
/// Input capture 1 filter
IC1F: enum(u4) {
/// No filter, sampling is done at fless thansub>DTSless than/sub>
B_0x0 = 0x0,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=2
B_0x1 = 0x1,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=4
B_0x2 = 0x2,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>tim_ker_ckless than/sub>, N=8
B_0x3 = 0x3,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=6
B_0x4 = 0x4,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/2, N=8
B_0x5 = 0x5,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=6
B_0x6 = 0x6,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/4, N=8
B_0x7 = 0x7,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=6
B_0x8 = 0x8,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/8, N=8
B_0x9 = 0x9,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=5
B_0xA = 0xa,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=6
B_0xB = 0xb,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/16, N=8
B_0xC = 0xc,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=5
B_0xD = 0xd,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=6
B_0xE = 0xe,
/// fless thansub>SAMPLINGless than/sub>=fless thansub>DTSless than/sub>/32, N=8
B_0xF = 0xf,
} = .B_0x0,
/// Capture/compare 2 selection
CC2S: enum(u2) {
/// CC2 channel is configured as output.
B_0x0 = 0x0,
/// CC2 channel is configured as input, tim_ic2 is mapped on tim_ti2.
B_0x1 = 0x1,
/// CC2 channel is configured as input, tim_ic2 is mapped on tim_ti1.
B_0x2 = 0x2,
/// CC2 channel is configured as input, tim_ic2 is mapped on tim_trc.
B_0x3 = 0x3,
} = .B_0x0,
/// Input capture 2 prescaler
IC2PSC: u2 = 0x0,
/// Input capture 2 filter
IC2F: u4 = 0x0,
padding: u16 = 0,
}),
/// TIM3 capture/compare mode register 2 [alternate]
/// offset: 0x1c
TIM3_CCMR2: mmio.Mmio(packed struct(u32) {
/// Capture/Compare 3 selection
CC3S: enum(u2) {
/// CC3 channel is configured as output
B_0x0 = 0x0,
/// CC3 channel is configured as input, tim_ic3 is mapped on tim_ti3
B_0x1 = 0x1,
/// CC3 channel is configured as input, tim_ic3 is mapped on tim_ti4
B_0x2 = 0x2,
/// CC3 channel is configured as input, tim_ic3 is mapped on tim_trc.
B_0x3 = 0x3,
} = .B_0x0,
/// Input capture 3 prescaler
IC3PSC: u2 = 0x0,
/// Input capture 3 filter
IC3F: u4 = 0x0,
/// Capture/Compare 4 selection
CC4S: enum(u2) {
/// CC4 channel is configured as output
B_0x0 = 0x0,
/// CC4 channel is configured as input, tim_ic4 is mapped on tim_ti4
B_0x1 = 0x1,
/// CC4 channel is configured as input, tim_ic4 is mapped on tim_ti3
B_0x2 = 0x2,
/// CC4 channel is configured as input, tim_ic4 is mapped on tim_trc.
B_0x3 = 0x3,
} = .B_0x0,
/// Input capture 4 prescaler
IC4PSC: u2 = 0x0,
/// Input capture 4 filter
IC4F: u4 = 0x0,
padding: u16 = 0,
}),
/// TIM3 capture/compare enable register
/// offset: 0x20
TIM3_CCER: mmio.Mmio(packed struct(u16) {
/// Capture/Compare 1 output enable.
CC1E: enum(u1) {
/// Capture mode disabled / OC1 is not active
B_0x0 = 0x0,
/// Capture mode enabled / OC1 signal is output on the corresponding output pin
B_0x1 = 0x1,
} = .B_0x0,
/// Capture/Compare 1 output Polarity.
CC1P: enum(u1) {
/// OC1 active high (output mode) / Edge sensitivity selection (input mode, see below)
B_0x0 = 0x0,
/// OC1 active low (output mode) / Edge sensitivity selection (input mode, see below)
B_0x1 = 0x1,
} = .B_0x0,
reserved3: u1 = 0,
/// Capture/Compare 1 output Polarity.
CC1NP: u1 = 0x0,
/// Capture/Compare 2 output enable.
CC2E: u1 = 0x0,
/// Capture/Compare 2 output Polarity.
CC2P: u1 = 0x0,
reserved7: u1 = 0,
/// Capture/Compare 2 output Polarity.
CC2NP: u1 = 0x0,
/// Capture/Compare 3 output enable.
CC3E: u1 = 0x0,
/// Capture/Compare 3 output Polarity.
CC3P: u1 = 0x0,
reserved11: u1 = 0,
/// Capture/Compare 3 output Polarity.
CC3NP: u1 = 0x0,
/// Capture/Compare 4 output enable.
CC4E: u1 = 0x0,
/// Capture/Compare 4 output Polarity.
CC4P: u1 = 0x0,
reserved15: u1 = 0,
/// Capture/Compare 4 output Polarity.
CC4NP: u1 = 0x0,
}),
/// offset: 0x22
reserved34: [2]u8,
/// TIM3 counter
/// offset: 0x24
TIM3_CNT: mmio.Mmio(packed struct(u32) {
/// Counter value
CNT: u16 = 0x0,
reserved31: u15 = 0,
/// Value depends on IUFREMAP in TIMx_CR1.
UIFCPY: u1 = 0x0,
}),
/// TIM3 prescaler
/// offset: 0x28
TIM3_PSC: mmio.Mmio(packed struct(u16) {
/// Prescaler value
PSC: u16 = 0x0,
}),
/// offset: 0x2a
reserved42: [2]u8,
/// TIM3 auto-reload register
/// offset: 0x2c
TIM3_ARR: mmio.Mmio(packed struct(u32) {
/// Low Auto-reload value
ARR: u20 = 0xFFFF,
padding: u12 = 0,
}),
/// offset: 0x30
reserved48: [4]u8,
/// TIM3 capture/compare register 1
/// offset: 0x34
TIM3_CCR1: mmio.Mmio(packed struct(u32) {
/// Capture/compare 1 value
CCR1: u20 = 0x0,
padding: u12 = 0,
}),
/// TIM3 capture/compare register 2
/// offset: 0x38
TIM3_CCR2: mmio.Mmio(packed struct(u32) {
/// Capture/compare 1 value
CCR2: u20 = 0x0,
padding: u12 = 0,
}),
/// TIM3 capture/compare register 3
/// offset: 0x3c
TIM3_CCR3: mmio.Mmio(packed struct(u32) {
/// Capture/compare 3 value
CCR3: u20 = 0x0,
padding: u12 = 0,
}),
/// TIM3 capture/compare register 4
/// offset: 0x40
TIM3_CCR4: mmio.Mmio(packed struct(u32) {
/// Capture/compare 4 value
CCR4: u20 = 0x0,
padding: u12 = 0,
}),
/// offset: 0x44
reserved68: [20]u8,
/// TIM3 timer encoder control register
/// offset: 0x58
TIM3_ECR: mmio.Mmio(packed struct(u32) {
/// Index enable
IE: enum(u1) {
/// Index disabled
B_0x0 = 0x0,
/// Index enabled
B_0x1 = 0x1,
} = .B_0x0,
/// Index direction
IDIR: enum(u2) {
/// Index resets the counter whatever the direction
B_0x0 = 0x0,
/// Index resets the counter when up-counting only
B_0x1 = 0x1,
/// Index resets the counter when down-counting only
B_0x2 = 0x2,
_,
} = .B_0x0,
reserved5: u2 = 0,
/// First index
FIDX: enum(u1) {
/// Index is always active
B_0x0 = 0x0,
/// the first Index only resets the counter
B_0x1 = 0x1,
} = .B_0x0,
/// Index positioning
IPOS: enum(u2) {
/// Index resets the counter when AB = 00
B_0x0 = 0x0,
/// Index resets the counter when AB = 01
B_0x1 = 0x1,
/// Index resets the counter when AB = 10
B_0x2 = 0x2,
/// Index resets the counter when AB = 11
B_0x3 = 0x3,
} = .B_0x0,
reserved16: u8 = 0,
/// Pulse width
PW: u8 = 0x0,
/// Pulse width prescaler
PWPRSC: u3 = 0x0,
padding: u5 = 0,
}),
/// TIM3 timer input selection register
/// offset: 0x5c
TIM3_TISEL: mmio.Mmio(packed struct(u32) {
/// Selects tim_ti1[15:0] input
TI1SEL: enum(u4) {
/// tim_ti1_in0: TIMx_CH1
B_0x0 = 0x0,
/// tim_ti1_in1
B_0x1 = 0x1,
/// tim_ti1_in15
B_0xF = 0xf,
_,
} = .B_0x0,
reserved8: u4 = 0,
/// Selects tim_ti2[15:0] input
TI2SEL: enum(u4) {
/// tim_ti2_in0: TIMx_CH2
B_0x0 = 0x0,
/// tim_ti2_in1
B_0x1 = 0x1,
/// tim_ti2_in15
B_0xF = 0xf,
_,
} = .B_0x0,
reserved16: u4 = 0,
/// Selects tim_ti3[15:0] input
TI3SEL: enum(u4) {
/// tim_ti3_in0: TIMx_CH3
B_0x0 = 0x0,
/// tim_ti3_in1
B_0x1 = 0x1,
/// tim_ti3_in15
B_0xF = 0xf,
_,
} = .B_0x0,
reserved24: u4 = 0,
/// Selects tim_ti4[15:0] input
TI4SEL: enum(u4) {
/// tim_ti4_in0: TIMx_CH4
B_0x0 = 0x0,
/// tim_ti4_in1
B_0x1 = 0x1,
/// tim_ti4_in15
B_0xF = 0xf,
_,
} = .B_0x0,
padding: u4 = 0,
}),
/// TIM3 alternate function register 1
/// offset: 0x60
TIM3_AF1: mmio.Mmio(packed struct(u32) {
reserved14: u14 = 0,
/// etr_in source selection
ETRSEL: enum(u4) {
/// tim_etr0: TIMx_ETR input
B_0x0 = 0x0,
/// tim_etr1
B_0x1 = 0x1,
/// tim_etr15
B_0xF = 0xf,
_,
} = .B_0x0,
padding: u14 = 0,
}),
/// TIM3 alternate function register 2
/// offset: 0x64
TIM3_AF2: mmio.Mmio(packed struct(u32) {
reserved16: u16 = 0,
/// ocref_clr source selection
OCRSEL: enum(u3) {
/// tim_ocref_clr0
B_0x0 = 0x0,
/// tim_ocref_clr1
B_0x1 = 0x1,
/// tim_ocref_clr7
B_0x7 = 0x7,
_,
} = .B_0x0,
padding: u13 = 0,
}),
/// offset: 0x68
reserved104: [884]u8,
/// TIM3 DMA control register
/// offset: 0x3dc
TIM3_DCR: mmio.Mmio(packed struct(u32) {
/// DMA base address
DBA: enum(u5) {
/// TIMx_CR1,
B_0x0 = 0x0,
/// TIMx_CR2,
B_0x1 = 0x1,
/// TIMx_SMCR,
B_0x2 = 0x2,
_,
} = .B_0x0,
reserved8: u3 = 0,
/// DMA burst length
DBL: enum(u5) {
/// 1 transfer
B_0x0 = 0x0,
/// 2 transfers
B_0x1 = 0x1,
/// 3 transfers
B_0x2 = 0x2,
/// 26 transfers
B_0x1A = 0x1a,
_,
} = .B_0x0,
padding: u19 = 0,
}),
/// TIM3 DMA address for full transfer
/// offset: 0x3e0
TIM3_DMAR: mmio.Mmio(packed struct(u32) {
/// DMA register for burst accesses
DMAB: u32 = 0x0,
}),
};

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src/stm32g4/types/peripherals/TIM6.zig Normal file
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const microzig = @import("microzig");
const mmio = microzig.mmio;
const types = @import("../../types.zig");
/// Basic-timers
pub const TIM6 = extern struct {
/// TIM6 control register 1
/// offset: 0x00
TIM6_CR1: mmio.Mmio(packed struct(u16) {
/// Counter enable
CEN: enum(u1) {
/// Counter disabled
B_0x0 = 0x0,
/// Counter enabled
B_0x1 = 0x1,
} = .B_0x0,
/// Update disable
UDIS: enum(u1) {
/// UEV enabled.
B_0x0 = 0x0,
/// UEV disabled.
B_0x1 = 0x1,
} = .B_0x0,
/// Update request source
URS: enum(u1) {
/// Any of the following events generates an update interrupt or DMA request if enabled.
B_0x0 = 0x0,
/// Only counter overflow/underflow generates an update interrupt or DMA request if enabled.
B_0x1 = 0x1,
} = .B_0x0,
/// One-pulse mode
OPM: enum(u1) {
/// Counter is not stopped at update event
B_0x0 = 0x0,
/// Counter stops counting at the next update event (clearing the CEN bit).
B_0x1 = 0x1,
} = .B_0x0,
reserved7: u3 = 0,
/// Auto-reload preload enable
ARPE: enum(u1) {
/// TIMx_ARR register is not buffered.
B_0x0 = 0x0,
/// TIMx_ARR register is buffered.
B_0x1 = 0x1,
} = .B_0x0,
reserved11: u3 = 0,
/// UIF status bit remapping
UIFREMAP: enum(u1) {
/// No remapping.
B_0x0 = 0x0,
/// Remapping enabled.
B_0x1 = 0x1,
} = .B_0x0,
/// Dithering enable
DITHEN: enum(u1) {
/// Dithering disabled
B_0x0 = 0x0,
/// Dithering enabled
B_0x1 = 0x1,
} = .B_0x0,
padding: u3 = 0,
}),
/// offset: 0x02
reserved2: [2]u8,
/// TIM6 control register 2
/// offset: 0x04
TIM6_CR2: mmio.Mmio(packed struct(u16) {
reserved4: u4 = 0,
/// Master mode selection
MMS: enum(u3) {
/// Reset - the UG bit from the TIMx_EGR register is used as a trigger output (tim_trgo).
B_0x0 = 0x0,
/// Enable - the Counter enable signal, tim_cnt_en, is used as a trigger output (tim_trgo).
B_0x1 = 0x1,
/// Update - The update event is selected as a trigger output (tim_trgo).
B_0x2 = 0x2,
_,
} = .B_0x0,
padding: u9 = 0,
}),
/// offset: 0x06
reserved6: [6]u8,
/// TIM6 DMA/Interrupt enable register
/// offset: 0x0c
TIM6_DIER: mmio.Mmio(packed struct(u16) {
/// Update interrupt enable
UIE: enum(u1) {
/// Update interrupt disabled.
B_0x0 = 0x0,
/// Update interrupt enabled.
B_0x1 = 0x1,
} = .B_0x0,
reserved8: u7 = 0,
/// Update DMA request enable
UDE: enum(u1) {
/// Update DMA request disabled.
B_0x0 = 0x0,
/// Update DMA request enabled.
B_0x1 = 0x1,
} = .B_0x0,
padding: u7 = 0,
}),
/// offset: 0x0e
reserved14: [2]u8,
/// TIM6 status register
/// offset: 0x10
TIM6_SR: mmio.Mmio(packed struct(u16) {
/// Update interrupt flag
UIF: enum(u1) {
/// No update occurred.
B_0x0 = 0x0,
/// Update interrupt pending.
B_0x1 = 0x1,
} = .B_0x0,
padding: u15 = 0,
}),
/// offset: 0x12
reserved18: [2]u8,
/// TIM6 event generation register
/// offset: 0x14
TIM6_EGR: mmio.Mmio(packed struct(u16) {
/// Update generation
UG: enum(u1) {
/// No action.
B_0x0 = 0x0,
/// Re-initializes the timer counter and generates an update of the registers.
B_0x1 = 0x1,
} = .B_0x0,
padding: u15 = 0,
}),
/// offset: 0x16
reserved22: [14]u8,
/// TIM6 counter
/// offset: 0x24
TIM6_CNT: mmio.Mmio(packed struct(u32) {
/// Counter value
CNT: u16 = 0x0,
reserved31: u15 = 0,
/// UIF copy
UIFCPY: u1 = 0x0,
}),
/// TIM6 prescaler
/// offset: 0x28
TIM6_PSC: mmio.Mmio(packed struct(u16) {
/// Prescaler value
PSC: u16 = 0x0,
}),
/// offset: 0x2a
reserved42: [2]u8,
/// TIM6 auto-reload register
/// offset: 0x2c
TIM6_ARR: mmio.Mmio(packed struct(u32) {
/// Auto-reload value
ARR: u20 = 0xFFFF,
padding: u12 = 0,
}),
};

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src/stm32g4/types/peripherals/UART4.zig Normal file
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const microzig = @import("microzig");
const mmio = microzig.mmio;
const types = @import("../../types.zig");
/// Universal synchronous asynchronous receiver transmitter
pub const UART4 = extern struct {
/// Control register 1
/// offset: 0x00
CR1: mmio.Mmio(packed struct(u32) {
/// USART enable
UE: u1 = 0x0,
/// USART enable in Stop mode
UESM: u1 = 0x0,
/// Receiver enable
RE: u1 = 0x0,
/// Transmitter enable
TE: u1 = 0x0,
/// IDLE interrupt enable
IDLEIE: u1 = 0x0,
/// RXNE interrupt enable
RXNEIE: u1 = 0x0,
/// Transmission complete interrupt enable
TCIE: u1 = 0x0,
/// interrupt enable
TXEIE: u1 = 0x0,
/// PE interrupt enable
PEIE: u1 = 0x0,
/// Parity selection
PS: u1 = 0x0,
/// Parity control enable
PCE: u1 = 0x0,
/// Receiver wakeup method
WAKE: u1 = 0x0,
/// Word length
M0: u1 = 0x0,
/// Mute mode enable
MME: u1 = 0x0,
/// Character match interrupt enable
CMIE: u1 = 0x0,
/// Oversampling mode
OVER8: u1 = 0x0,
/// DEDT0
DEDT0: u1 = 0x0,
/// DEDT1
DEDT1: u1 = 0x0,
/// DEDT2
DEDT2: u1 = 0x0,
/// DEDT3
DEDT3: u1 = 0x0,
/// Driver Enable de-assertion time
DEDT4: u1 = 0x0,
/// DEAT0
DEAT0: u1 = 0x0,
/// DEAT1
DEAT1: u1 = 0x0,
/// DEAT2
DEAT2: u1 = 0x0,
/// DEAT3
DEAT3: u1 = 0x0,
/// Driver Enable assertion time
DEAT4: u1 = 0x0,
/// Receiver timeout interrupt enable
RTOIE: u1 = 0x0,
/// End of Block interrupt enable
EOBIE: u1 = 0x0,
/// M1
M1: u1 = 0x0,
/// FIFOEN
FIFOEN: u1 = 0x0,
/// TXFEIE
TXFEIE: u1 = 0x0,
/// RXFFIE
RXFFIE: u1 = 0x0,
}),
/// Control register 2
/// offset: 0x04
CR2: mmio.Mmio(packed struct(u32) {
/// SLVEN
SLVEN: u1 = 0x0,
reserved3: u2 = 0,
/// DIS_NSS
DIS_NSS: u1 = 0x0,
/// 7-bit Address Detection/4-bit Address Detection
ADDM7: u1 = 0x0,
/// LIN break detection length
LBDL: u1 = 0x0,
/// LIN break detection interrupt enable
LBDIE: u1 = 0x0,
reserved8: u1 = 0,
/// Last bit clock pulse
LBCL: u1 = 0x0,
/// Clock phase
CPHA: u1 = 0x0,
/// Clock polarity
CPOL: u1 = 0x0,
/// Clock enable
CLKEN: u1 = 0x0,
/// STOP bits
STOP: u2 = 0x0,
/// LIN mode enable
LINEN: u1 = 0x0,
/// Swap TX/RX pins
SWAP: u1 = 0x0,
/// RX pin active level inversion
RXINV: u1 = 0x0,
/// TX pin active level inversion
TXINV: u1 = 0x0,
/// Binary data inversion
TAINV: u1 = 0x0,
/// Most significant bit first
MSBFIRST: u1 = 0x0,
/// Auto baud rate enable
ABREN: u1 = 0x0,
/// ABRMOD0
ABRMOD0: u1 = 0x0,
/// Auto baud rate mode
ABRMOD1: u1 = 0x0,
/// Receiver timeout enable
RTOEN: u1 = 0x0,
/// Address of the USART node
ADD0_3: u4 = 0x0,
/// Address of the USART node
ADD4_7: u4 = 0x0,
}),
/// Control register 3
/// offset: 0x08
CR3: mmio.Mmio(packed struct(u32) {
/// Error interrupt enable
EIE: u1 = 0x0,
/// Ir mode enable
IREN: u1 = 0x0,
/// Ir low-power
IRLP: u1 = 0x0,
/// Half-duplex selection
HDSEL: u1 = 0x0,
/// Smartcard NACK enable
NACK: u1 = 0x0,
/// Smartcard mode enable
SCEN: u1 = 0x0,
/// DMA enable receiver
DMAR: u1 = 0x0,
/// DMA enable transmitter
DMAT: u1 = 0x0,
/// RTS enable
RTSE: u1 = 0x0,
/// CTS enable
CTSE: u1 = 0x0,
/// CTS interrupt enable
CTSIE: u1 = 0x0,
/// One sample bit method enable
ONEBIT: u1 = 0x0,
/// Overrun Disable
OVRDIS: u1 = 0x0,
/// DMA Disable on Reception Error
DDRE: u1 = 0x0,
/// Driver enable mode
DEM: u1 = 0x0,
/// Driver enable polarity selection
DEP: u1 = 0x0,
reserved17: u1 = 0,
/// Smartcard auto-retry count
SCARCNT: u3 = 0x0,
/// Wakeup from Stop mode interrupt flag selection
WUS: u2 = 0x0,
/// Wakeup from Stop mode interrupt enable
WUFIE: u1 = 0x0,
/// TXFTIE
TXFTIE: u1 = 0x0,
/// TCBGTIE
TCBGTIE: u1 = 0x0,
/// RXFTCFG
RXFTCFG: u3 = 0x0,
/// RXFTIE
RXFTIE: u1 = 0x0,
/// TXFTCFG
TXFTCFG: u3 = 0x0,
}),
/// Baud rate register
/// offset: 0x0c
BRR: mmio.Mmio(packed struct(u32) {
/// DIV_Fraction
DIV_Fraction: u4 = 0x0,
/// DIV_Mantissa
DIV_Mantissa: u12 = 0x0,
padding: u16 = 0,
}),
/// Guard time and prescaler register
/// offset: 0x10
GTPR: mmio.Mmio(packed struct(u32) {
/// Prescaler value
PSC: u8 = 0x0,
/// Guard time value
GT: u8 = 0x0,
padding: u16 = 0,
}),
/// Receiver timeout register
/// offset: 0x14
RTOR: mmio.Mmio(packed struct(u32) {
/// Receiver timeout value
RTO: u24 = 0x0,
/// Block Length
BLEN: u8 = 0x0,
}),
/// Request register
/// offset: 0x18
RQR: mmio.Mmio(packed struct(u32) {
/// Auto baud rate request
ABRRQ: u1 = 0x0,
/// Send break request
SBKRQ: u1 = 0x0,
/// Mute mode request
MMRQ: u1 = 0x0,
/// Receive data flush request
RXFRQ: u1 = 0x0,
/// Transmit data flush request
TXFRQ: u1 = 0x0,
padding: u27 = 0,
}),
/// Interrupt & status register
/// offset: 0x1c
ISR: mmio.Mmio(packed struct(u32) {
/// PE
PE: u1 = 0x0,
/// FE
FE: u1 = 0x0,
/// NF
NF: u1 = 0x0,
/// ORE
ORE: u1 = 0x0,
/// IDLE
IDLE: u1 = 0x0,
/// RXNE
RXNE: u1 = 0x0,
/// TC
TC: u1 = 0x1,
/// TXE
TXE: u1 = 0x1,
/// LBDF
LBDF: u1 = 0x0,
/// CTSIF
CTSIF: u1 = 0x0,
/// CTS
CTS: u1 = 0x0,
/// RTOF
RTOF: u1 = 0x0,
/// EOBF
EOBF: u1 = 0x0,
/// UDR
UDR: u1 = 0x0,
/// ABRE
ABRE: u1 = 0x0,
/// ABRF
ABRF: u1 = 0x0,
/// BUSY
BUSY: u1 = 0x0,
/// CMF
CMF: u1 = 0x0,
/// SBKF
SBKF: u1 = 0x0,
/// RWU
RWU: u1 = 0x0,
/// WUF
WUF: u1 = 0x0,
/// TEACK
TEACK: u1 = 0x0,
/// REACK
REACK: u1 = 0x0,
/// TXFE
TXFE: u1 = 0x0,
/// RXFF
RXFF: u1 = 0x0,
/// TCBGT
TCBGT: u1 = 0x0,
/// RXFT
RXFT: u1 = 0x0,
/// TXFT
TXFT: u1 = 0x0,
padding: u4 = 0,
}),
/// Interrupt flag clear register
/// offset: 0x20
ICR: mmio.Mmio(packed struct(u32) {
/// Parity error clear flag
PECF: u1 = 0x0,
/// Framing error clear flag
FECF: u1 = 0x0,
/// Noise detected clear flag
NCF: u1 = 0x0,
/// Overrun error clear flag
ORECF: u1 = 0x0,
/// Idle line detected clear flag
IDLECF: u1 = 0x0,
/// TXFECF
TXFECF: u1 = 0x0,
/// Transmission complete clear flag
TCCF: u1 = 0x0,
/// TCBGTCF
TCBGTCF: u1 = 0x0,
/// LIN break detection clear flag
LBDCF: u1 = 0x0,
/// CTS clear flag
CTSCF: u1 = 0x0,
reserved11: u1 = 0,
/// Receiver timeout clear flag
RTOCF: u1 = 0x0,
/// End of block clear flag
EOBCF: u1 = 0x0,
/// UDRCF
UDRCF: u1 = 0x0,
reserved17: u3 = 0,
/// Character match clear flag
CMCF: u1 = 0x0,
reserved20: u2 = 0,
/// Wakeup from Stop mode clear flag
WUCF: u1 = 0x0,
padding: u11 = 0,
}),
/// Receive data register
/// offset: 0x24
RDR: mmio.Mmio(packed struct(u32) {
/// Receive data value
RDR: u9 = 0x0,
padding: u23 = 0,
}),
/// Transmit data register
/// offset: 0x28
TDR: mmio.Mmio(packed struct(u32) {
/// Transmit data value
TDR: u9 = 0x0,
padding: u23 = 0,
}),
/// USART prescaler register
/// offset: 0x2c
PRESC: mmio.Mmio(packed struct(u32) {
/// PRESCALER
PRESCALER: u4 = 0x0,
padding: u28 = 0,
}),
};

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src/stm32g4/types/peripherals/UCPD1.zig Normal file
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const microzig = @import("microzig");
const mmio = microzig.mmio;
const types = @import("../../types.zig");
/// UCPD1
pub const UCPD1 = extern struct {
/// UCPD configuration register 1
/// offset: 0x00
CFG1: mmio.Mmio(packed struct(u32) {
/// HBITCLKDIV
HBITCLKDIV: u6 = 0x0,
/// IFRGAP
IFRGAP: u5 = 0x0,
/// TRANSWIN
TRANSWIN: u5 = 0x0,
reserved17: u1 = 0,
/// PSC_USBPDCLK
PSC_USBPDCLK: u3 = 0x0,
/// RXORDSETEN
RXORDSETEN: u9 = 0x0,
/// TXDMAEN
TXDMAEN: u1 = 0x0,
/// RXDMAEN
RXDMAEN: u1 = 0x0,
/// UCPDEN
UCPDEN: u1 = 0x0,
}),
/// UCPD configuration register 2
/// offset: 0x04
CFG2: mmio.Mmio(packed struct(u32) {
/// RXFILTDIS
RXFILTDIS: u1 = 0x0,
/// RXFILT2N3
RXFILT2N3: u1 = 0x0,
/// FORCECLK
FORCECLK: u1 = 0x0,
/// WUPEN
WUPEN: u1 = 0x0,
padding: u28 = 0,
}),
/// offset: 0x08
reserved8: [4]u8,
/// UCPD configuration register 2
/// offset: 0x0c
CR: mmio.Mmio(packed struct(u32) {
/// TXMODE
TXMODE: u2 = 0x0,
/// TXSEND
TXSEND: u1 = 0x0,
/// TXHRST
TXHRST: u1 = 0x0,
/// RXMODE
RXMODE: u1 = 0x0,
/// PHYRXEN
PHYRXEN: u1 = 0x0,
/// PHYCCSEL
PHYCCSEL: u1 = 0x0,
/// ANASUBMODE
ANASUBMODE: u2 = 0x0,
/// ANAMODE
ANAMODE: u1 = 0x0,
/// CCENABLE
CCENABLE: u2 = 0x0,
reserved16: u4 = 0,
/// FRSRXEN
FRSRXEN: u1 = 0x0,
/// FRSTX
FRSTX: u1 = 0x0,
/// RDCH
RDCH: u1 = 0x0,
reserved20: u1 = 0,
/// CC1TCDIS
CC1TCDIS: u1 = 0x0,
/// CC2TCDIS
CC2TCDIS: u1 = 0x0,
padding: u10 = 0,
}),
/// UCPD Interrupt Mask Register
/// offset: 0x10
IMR: mmio.Mmio(packed struct(u32) {
/// TXISIE
TXISIE: u1 = 0x0,
/// TXMSGDISCIE
TXMSGDISCIE: u1 = 0x0,
/// TXMSGSENTIE
TXMSGSENTIE: u1 = 0x0,
/// TXMSGABTIE
TXMSGABTIE: u1 = 0x0,
/// HRSTDISCIE
HRSTDISCIE: u1 = 0x0,
/// HRSTSENTIE
HRSTSENTIE: u1 = 0x0,
/// TXUNDIE
TXUNDIE: u1 = 0x0,
reserved8: u1 = 0,
/// RXNEIE
RXNEIE: u1 = 0x0,
/// RXORDDETIE
RXORDDETIE: u1 = 0x0,
/// RXHRSTDETIE
RXHRSTDETIE: u1 = 0x0,
/// RXOVRIE
RXOVRIE: u1 = 0x0,
/// RXMSGENDIE
RXMSGENDIE: u1 = 0x0,
reserved14: u1 = 0,
/// TYPECEVT1IE
TYPECEVT1IE: u1 = 0x0,
/// TYPECEVT2IE
TYPECEVT2IE: u1 = 0x0,
reserved20: u4 = 0,
/// FRSEVTIE
FRSEVTIE: u1 = 0x0,
padding: u11 = 0,
}),
/// UCPD Status Register
/// offset: 0x14
SR: mmio.Mmio(packed struct(u32) {
/// TXIS
TXIS: u1 = 0x0,
/// TXMSGDISC
TXMSGDISC: u1 = 0x0,
/// TXMSGSENT
TXMSGSENT: u1 = 0x0,
/// TXMSGABT
TXMSGABT: u1 = 0x0,
/// HRSTDISC
HRSTDISC: u1 = 0x0,
/// HRSTSENT
HRSTSENT: u1 = 0x0,
/// TXUND
TXUND: u1 = 0x0,
reserved8: u1 = 0,
/// RXNE
RXNE: u1 = 0x0,
/// RXORDDET
RXORDDET: u1 = 0x0,
/// RXHRSTDET
RXHRSTDET: u1 = 0x0,
/// RXOVR
RXOVR: u1 = 0x0,
/// RXMSGEND
RXMSGEND: u1 = 0x0,
/// RXERR
RXERR: u1 = 0x0,
/// TYPECEVT1
TYPECEVT1: u1 = 0x0,
/// TYPECEVT2
TYPECEVT2: u1 = 0x0,
/// TYPEC_VSTATE_CC1
TYPEC_VSTATE_CC1: u2 = 0x0,
/// TYPEC_VSTATE_CC2
TYPEC_VSTATE_CC2: u2 = 0x0,
/// FRSEVT
FRSEVT: u1 = 0x0,
padding: u11 = 0,
}),
/// UCPD Interrupt Clear Register
/// offset: 0x18
ICR: mmio.Mmio(packed struct(u32) {
reserved1: u1 = 0,
/// TXMSGDISCCF
TXMSGDISCCF: u1 = 0x0,
/// TXMSGSENTCF
TXMSGSENTCF: u1 = 0x0,
/// TXMSGABTCF
TXMSGABTCF: u1 = 0x0,
/// HRSTDISCCF
HRSTDISCCF: u1 = 0x0,
/// HRSTSENTCF
HRSTSENTCF: u1 = 0x0,
/// TXUNDCF
TXUNDCF: u1 = 0x0,
reserved9: u2 = 0,
/// RXORDDETCF
RXORDDETCF: u1 = 0x0,
/// RXHRSTDETCF
RXHRSTDETCF: u1 = 0x0,
/// RXOVRCF
RXOVRCF: u1 = 0x0,
/// RXMSGENDCF
RXMSGENDCF: u1 = 0x0,
reserved14: u1 = 0,
/// TYPECEVT1CF
TYPECEVT1CF: u1 = 0x0,
/// TYPECEVT2CF
TYPECEVT2CF: u1 = 0x0,
reserved20: u4 = 0,
/// FRSEVTCF
FRSEVTCF: u1 = 0x0,
padding: u11 = 0,
}),
/// UCPD Tx Ordered Set Type Register
/// offset: 0x1c
TX_ORDSET: mmio.Mmio(packed struct(u32) {
/// TXORDSET
TXORDSET: u20 = 0x0,
padding: u12 = 0,
}),
/// UCPD Tx Paysize Register
/// offset: 0x20
TX_PAYSZ: mmio.Mmio(packed struct(u32) {
/// TXPAYSZ
TXPAYSZ: u10 = 0x0,
padding: u22 = 0,
}),
/// UCPD Tx Data Register
/// offset: 0x24
TXDR: mmio.Mmio(packed struct(u32) {
/// TXDATA
TXDATA: u8 = 0x0,
padding: u24 = 0,
}),
/// UCPD Rx Ordered Set Register
/// offset: 0x28
RX_ORDSET: mmio.Mmio(packed struct(u32) {
/// RXORDSET
RXORDSET: u3 = 0x0,
/// RXSOP3OF4
RXSOP3OF4: u1 = 0x0,
/// RXSOPKINVALID
RXSOPKINVALID: u3 = 0x0,
padding: u25 = 0,
}),
/// UCPD Rx Paysize Register
/// offset: 0x2c
RX_PAYSZ: mmio.Mmio(packed struct(u32) {
/// RXPAYSZ
RXPAYSZ: u10 = 0x0,
padding: u22 = 0,
}),
/// UCPD Rx Data Register
/// offset: 0x30
RXDR: mmio.Mmio(packed struct(u32) {
/// RXDATA
RXDATA: u8 = 0x0,
padding: u24 = 0,
}),
/// UCPD Rx Ordered Set Extension Register 1
/// offset: 0x34
RX_ORDEXT1: mmio.Mmio(packed struct(u32) {
/// RXSOPX1
RXSOPX1: u20 = 0x0,
padding: u12 = 0,
}),
/// UCPD Rx Ordered Set Extension Register 2
/// offset: 0x38
RX_ORDEXT2: mmio.Mmio(packed struct(u32) {
/// RXSOPX2
RXSOPX2: u20 = 0x0,
padding: u12 = 0,
}),
};

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src/stm32g4/types/peripherals/USART1.zig Normal file
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const microzig = @import("microzig");
const mmio = microzig.mmio;
const types = @import("../../types.zig");
/// Universal synchronous asynchronous receiver transmitter
pub const USART1 = extern struct {
/// Control register 1
/// offset: 0x00
CR1: mmio.Mmio(packed struct(u32) {
/// USART enable
UE: u1 = 0x0,
/// USART enable in Stop mode
UESM: u1 = 0x0,
/// Receiver enable
RE: u1 = 0x0,
/// Transmitter enable
TE: u1 = 0x0,
/// IDLE interrupt enable
IDLEIE: u1 = 0x0,
/// RXNE interrupt enable
RXNEIE: u1 = 0x0,
/// Transmission complete interrupt enable
TCIE: u1 = 0x0,
/// interrupt enable
TXEIE: u1 = 0x0,
/// PE interrupt enable
PEIE: u1 = 0x0,
/// Parity selection
PS: u1 = 0x0,
/// Parity control enable
PCE: u1 = 0x0,
/// Receiver wakeup method
WAKE: u1 = 0x0,
/// Word length
M0: u1 = 0x0,
/// Mute mode enable
MME: u1 = 0x0,
/// Character match interrupt enable
CMIE: u1 = 0x0,
/// Oversampling mode
OVER8: u1 = 0x0,
/// DEDT0
DEDT0: u1 = 0x0,
/// DEDT1
DEDT1: u1 = 0x0,
/// DEDT2
DEDT2: u1 = 0x0,
/// DEDT3
DEDT3: u1 = 0x0,
/// Driver Enable de-assertion time
DEDT4: u1 = 0x0,
/// DEAT0
DEAT0: u1 = 0x0,
/// DEAT1
DEAT1: u1 = 0x0,
/// DEAT2
DEAT2: u1 = 0x0,
/// DEAT3
DEAT3: u1 = 0x0,
/// Driver Enable assertion time
DEAT4: u1 = 0x0,
/// Receiver timeout interrupt enable
RTOIE: u1 = 0x0,
/// End of Block interrupt enable
EOBIE: u1 = 0x0,
/// M1
M1: u1 = 0x0,
/// FIFOEN
FIFOEN: u1 = 0x0,
/// TXFEIE
TXFEIE: u1 = 0x0,
/// RXFFIE
RXFFIE: u1 = 0x0,
}),
/// Control register 2
/// offset: 0x04
CR2: mmio.Mmio(packed struct(u32) {
/// SLVEN
SLVEN: u1 = 0x0,
reserved3: u2 = 0,
/// DIS_NSS
DIS_NSS: u1 = 0x0,
/// 7-bit Address Detection/4-bit Address Detection
ADDM7: u1 = 0x0,
/// LIN break detection length
LBDL: u1 = 0x0,
/// LIN break detection interrupt enable
LBDIE: u1 = 0x0,
reserved8: u1 = 0,
/// Last bit clock pulse
LBCL: u1 = 0x0,
/// Clock phase
CPHA: u1 = 0x0,
/// Clock polarity
CPOL: u1 = 0x0,
/// Clock enable
CLKEN: u1 = 0x0,
/// STOP bits
STOP: u2 = 0x0,
/// LIN mode enable
LINEN: u1 = 0x0,
/// Swap TX/RX pins
SWAP: u1 = 0x0,
/// RX pin active level inversion
RXINV: u1 = 0x0,
/// TX pin active level inversion
TXINV: u1 = 0x0,
/// Binary data inversion
TAINV: u1 = 0x0,
/// Most significant bit first
MSBFIRST: u1 = 0x0,
/// Auto baud rate enable
ABREN: u1 = 0x0,
/// ABRMOD0
ABRMOD0: u1 = 0x0,
/// Auto baud rate mode
ABRMOD1: u1 = 0x0,
/// Receiver timeout enable
RTOEN: u1 = 0x0,
/// Address of the USART node
ADD0_3: u4 = 0x0,
/// Address of the USART node
ADD4_7: u4 = 0x0,
}),
/// Control register 3
/// offset: 0x08
CR3: mmio.Mmio(packed struct(u32) {
/// Error interrupt enable
EIE: u1 = 0x0,
/// Ir mode enable
IREN: u1 = 0x0,
/// Ir low-power
IRLP: u1 = 0x0,
/// Half-duplex selection
HDSEL: u1 = 0x0,
/// Smartcard NACK enable
NACK: u1 = 0x0,
/// Smartcard mode enable
SCEN: u1 = 0x0,
/// DMA enable receiver
DMAR: u1 = 0x0,
/// DMA enable transmitter
DMAT: u1 = 0x0,
/// RTS enable
RTSE: u1 = 0x0,
/// CTS enable
CTSE: u1 = 0x0,
/// CTS interrupt enable
CTSIE: u1 = 0x0,
/// One sample bit method enable
ONEBIT: u1 = 0x0,
/// Overrun Disable
OVRDIS: u1 = 0x0,
/// DMA Disable on Reception Error
DDRE: u1 = 0x0,
/// Driver enable mode
DEM: u1 = 0x0,
/// Driver enable polarity selection
DEP: u1 = 0x0,
reserved17: u1 = 0,
/// Smartcard auto-retry count
SCARCNT: u3 = 0x0,
/// Wakeup from Stop mode interrupt flag selection
WUS: u2 = 0x0,
/// Wakeup from Stop mode interrupt enable
WUFIE: u1 = 0x0,
/// TXFTIE
TXFTIE: u1 = 0x0,
/// TCBGTIE
TCBGTIE: u1 = 0x0,
/// RXFTCFG
RXFTCFG: u3 = 0x0,
/// RXFTIE
RXFTIE: u1 = 0x0,
/// TXFTCFG
TXFTCFG: u3 = 0x0,
}),
/// Baud rate register
/// offset: 0x0c
BRR: mmio.Mmio(packed struct(u32) {
/// DIV_Fraction
DIV_Fraction: u4 = 0x0,
/// DIV_Mantissa
DIV_Mantissa: u12 = 0x0,
padding: u16 = 0,
}),
/// Guard time and prescaler register
/// offset: 0x10
GTPR: mmio.Mmio(packed struct(u32) {
/// Prescaler value
PSC: u8 = 0x0,
/// Guard time value
GT: u8 = 0x0,
padding: u16 = 0,
}),
/// Receiver timeout register
/// offset: 0x14
RTOR: mmio.Mmio(packed struct(u32) {
/// Receiver timeout value
RTO: u24 = 0x0,
/// Block Length
BLEN: u8 = 0x0,
}),
/// Request register
/// offset: 0x18
RQR: mmio.Mmio(packed struct(u32) {
/// Auto baud rate request
ABRRQ: u1 = 0x0,
/// Send break request
SBKRQ: u1 = 0x0,
/// Mute mode request
MMRQ: u1 = 0x0,
/// Receive data flush request
RXFRQ: u1 = 0x0,
/// Transmit data flush request
TXFRQ: u1 = 0x0,
padding: u27 = 0,
}),
/// Interrupt & status register
/// offset: 0x1c
ISR: mmio.Mmio(packed struct(u32) {
/// PE
PE: u1 = 0x0,
/// FE
FE: u1 = 0x0,
/// NF
NF: u1 = 0x0,
/// ORE
ORE: u1 = 0x0,
/// IDLE
IDLE: u1 = 0x0,
/// RXNE
RXNE: u1 = 0x0,
/// TC
TC: u1 = 0x0,
/// TXE
TXE: u1 = 0x0,
/// LBDF
LBDF: u1 = 0x0,
/// CTSIF
CTSIF: u1 = 0x0,
/// CTS
CTS: u1 = 0x0,
/// RTOF
RTOF: u1 = 0x0,
/// EOBF
EOBF: u1 = 0x0,
/// UDR
UDR: u1 = 0x0,
/// ABRE
ABRE: u1 = 0x0,
/// ABRF
ABRF: u1 = 0x0,
/// BUSY
BUSY: u1 = 0x0,
/// CMF
CMF: u1 = 0x0,
/// SBKF
SBKF: u1 = 0x0,
/// RWU
RWU: u1 = 0x0,
/// WUF
WUF: u1 = 0x0,
/// TEACK
TEACK: u1 = 0x0,
/// REACK
REACK: u1 = 0x0,
/// TXFE
TXFE: u1 = 0x0,
/// RXFF
RXFF: u1 = 0x0,
/// TCBGT
TCBGT: u1 = 0x0,
/// RXFT
RXFT: u1 = 0x0,
/// TXFT
TXFT: u1 = 0x0,
padding: u4 = 0,
}),
/// Interrupt flag clear register
/// offset: 0x20
ICR: mmio.Mmio(packed struct(u32) {
/// Parity error clear flag
PECF: u1 = 0x0,
/// Framing error clear flag
FECF: u1 = 0x0,
/// Noise detected clear flag
NCF: u1 = 0x0,
/// Overrun error clear flag
ORECF: u1 = 0x0,
/// Idle line detected clear flag
IDLECF: u1 = 0x0,
/// TXFECF
TXFECF: u1 = 0x0,
/// Transmission complete clear flag
TCCF: u1 = 0x0,
/// TCBGTCF
TCBGTCF: u1 = 0x0,
/// LIN break detection clear flag
LBDCF: u1 = 0x0,
/// CTS clear flag
CTSCF: u1 = 0x0,
reserved11: u1 = 0,
/// Receiver timeout clear flag
RTOCF: u1 = 0x0,
/// End of block clear flag
EOBCF: u1 = 0x0,
/// UDRCF
UDRCF: u1 = 0x0,
reserved17: u3 = 0,
/// Character match clear flag
CMCF: u1 = 0x0,
reserved20: u2 = 0,
/// Wakeup from Stop mode clear flag
WUCF: u1 = 0x0,
padding: u11 = 0,
}),
/// Receive data register
/// offset: 0x24
RDR: mmio.Mmio(packed struct(u32) {
/// Receive data value
RDR: u9 = 0x0,
padding: u23 = 0,
}),
/// Transmit data register
/// offset: 0x28
TDR: mmio.Mmio(packed struct(u32) {
/// Transmit data value
TDR: u9 = 0x0,
padding: u23 = 0,
}),
/// USART prescaler register
/// offset: 0x2c
PRESC: mmio.Mmio(packed struct(u32) {
/// PRESCALER
PRESCALER: u4 = 0x0,
padding: u28 = 0,
}),
};

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src/stm32g4/types/peripherals/USB_FS_device.zig Normal file
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const microzig = @import("microzig");
const mmio = microzig.mmio;
const types = @import("../../types.zig");
/// USB_FS_device
pub const USB_FS_device = extern struct {
/// USB endpoint n register
/// offset: 0x00
EP0R: mmio.Mmio(packed struct(u32) {
/// EA
EA: u4 = 0x0,
/// STAT_TX
STAT_TX: u2 = 0x0,
/// DTOG_TX
DTOG_TX: u1 = 0x0,
/// CTR_TX
CTR_TX: u1 = 0x0,
/// EP_KIND
EP_KIND: u1 = 0x0,
/// EP_TYPE
EP_TYPE: u2 = 0x0,
/// SETUP
SETUP: u1 = 0x0,
/// STAT_RX
STAT_RX: u2 = 0x0,
/// DTOG_RX
DTOG_RX: u1 = 0x0,
/// CTR_RX
CTR_RX: u1 = 0x0,
padding: u16 = 0,
}),
/// USB endpoint n register
/// offset: 0x04
EP1R: mmio.Mmio(packed struct(u32) {
/// EA
EA: u4 = 0x0,
/// STAT_TX
STAT_TX: u2 = 0x0,
/// DTOG_TX
DTOG_TX: u1 = 0x0,
/// CTR_TX
CTR_TX: u1 = 0x0,
/// EP_KIND
EP_KIND: u1 = 0x0,
/// EP_TYPE
EP_TYPE: u2 = 0x0,
/// SETUP
SETUP: u1 = 0x0,
/// STAT_RX
STAT_RX: u2 = 0x0,
/// DTOG_RX
DTOG_RX: u1 = 0x0,
/// CTR_RX
CTR_RX: u1 = 0x0,
padding: u16 = 0,
}),
/// USB endpoint n register
/// offset: 0x08
EP2R: mmio.Mmio(packed struct(u32) {
/// EA
EA: u4 = 0x0,
/// STAT_TX
STAT_TX: u2 = 0x0,
/// DTOG_TX
DTOG_TX: u1 = 0x0,
/// CTR_TX
CTR_TX: u1 = 0x0,
/// EP_KIND
EP_KIND: u1 = 0x0,
/// EP_TYPE
EP_TYPE: u2 = 0x0,
/// SETUP
SETUP: u1 = 0x0,
/// STAT_RX
STAT_RX: u2 = 0x0,
/// DTOG_RX
DTOG_RX: u1 = 0x0,
/// CTR_RX
CTR_RX: u1 = 0x0,
padding: u16 = 0,
}),
/// USB endpoint n register
/// offset: 0x0c
EP3R: mmio.Mmio(packed struct(u32) {
/// EA
EA: u4 = 0x0,
/// STAT_TX
STAT_TX: u2 = 0x0,
/// DTOG_TX
DTOG_TX: u1 = 0x0,
/// CTR_TX
CTR_TX: u1 = 0x0,
/// EP_KIND
EP_KIND: u1 = 0x0,
/// EP_TYPE
EP_TYPE: u2 = 0x0,
/// SETUP
SETUP: u1 = 0x0,
/// STAT_RX
STAT_RX: u2 = 0x0,
/// DTOG_RX
DTOG_RX: u1 = 0x0,
/// CTR_RX
CTR_RX: u1 = 0x0,
padding: u16 = 0,
}),
/// USB endpoint n register
/// offset: 0x10
EP4R: mmio.Mmio(packed struct(u32) {
/// EA
EA: u4 = 0x0,
/// STAT_TX
STAT_TX: u2 = 0x0,
/// DTOG_TX
DTOG_TX: u1 = 0x0,
/// CTR_TX
CTR_TX: u1 = 0x0,
/// EP_KIND
EP_KIND: u1 = 0x0,
/// EP_TYPE
EP_TYPE: u2 = 0x0,
/// SETUP
SETUP: u1 = 0x0,
/// STAT_RX
STAT_RX: u2 = 0x0,
/// DTOG_RX
DTOG_RX: u1 = 0x0,
/// CTR_RX
CTR_RX: u1 = 0x0,
padding: u16 = 0,
}),
/// USB endpoint n register
/// offset: 0x14
EP5R: mmio.Mmio(packed struct(u32) {
/// EA
EA: u4 = 0x0,
/// STAT_TX
STAT_TX: u2 = 0x0,
/// DTOG_TX
DTOG_TX: u1 = 0x0,
/// CTR_TX
CTR_TX: u1 = 0x0,
/// EP_KIND
EP_KIND: u1 = 0x0,
/// EP_TYPE
EP_TYPE: u2 = 0x0,
/// SETUP
SETUP: u1 = 0x0,
/// STAT_RX
STAT_RX: u2 = 0x0,
/// DTOG_RX
DTOG_RX: u1 = 0x0,
/// CTR_RX
CTR_RX: u1 = 0x0,
padding: u16 = 0,
}),
/// USB endpoint n register
/// offset: 0x18
EP6R: mmio.Mmio(packed struct(u32) {
/// EA
EA: u4 = 0x0,
/// STAT_TX
STAT_TX: u2 = 0x0,
/// DTOG_TX
DTOG_TX: u1 = 0x0,
/// CTR_TX
CTR_TX: u1 = 0x0,
/// EP_KIND
EP_KIND: u1 = 0x0,
/// EP_TYPE
EP_TYPE: u2 = 0x0,
/// SETUP
SETUP: u1 = 0x0,
/// STAT_RX
STAT_RX: u2 = 0x0,
/// DTOG_RX
DTOG_RX: u1 = 0x0,
/// CTR_RX
CTR_RX: u1 = 0x0,
padding: u16 = 0,
}),
/// USB endpoint n register
/// offset: 0x1c
EP7R: mmio.Mmio(packed struct(u32) {
/// EA
EA: u4 = 0x0,
/// STAT_TX
STAT_TX: u2 = 0x0,
/// DTOG_TX
DTOG_TX: u1 = 0x0,
/// CTR_TX
CTR_TX: u1 = 0x0,
/// EP_KIND
EP_KIND: u1 = 0x0,
/// EP_TYPE
EP_TYPE: u2 = 0x0,
/// SETUP
SETUP: u1 = 0x0,
/// STAT_RX
STAT_RX: u2 = 0x0,
/// DTOG_RX
DTOG_RX: u1 = 0x0,
/// CTR_RX
CTR_RX: u1 = 0x0,
padding: u16 = 0,
}),
/// offset: 0x20
reserved32: [32]u8,
/// USB control register
/// offset: 0x40
CNTR: mmio.Mmio(packed struct(u32) {
/// FRES
FRES: u1 = 0x0,
/// PDWN
PDWN: u1 = 0x0,
/// LP_MODE
LP_MODE: u1 = 0x0,
/// FSUSP
FSUSP: u1 = 0x0,
/// RESUME
RESUME: u1 = 0x0,
/// L1RESUME
L1RESUME: u1 = 0x0,
reserved7: u1 = 0,
/// L1REQM
L1REQM: u1 = 0x0,
/// ESOFM
ESOFM: u1 = 0x0,
/// SOFM
SOFM: u1 = 0x0,
/// RESETM
RESETM: u1 = 0x0,
/// SUSPM
SUSPM: u1 = 0x0,
/// WKUPM
WKUPM: u1 = 0x0,
/// ERRM
ERRM: u1 = 0x0,
/// PMAOVRM
PMAOVRM: u1 = 0x0,
/// CTRM
CTRM: u1 = 0x0,
padding: u16 = 0,
}),
/// USB interrupt status register
/// offset: 0x44
ISTR: mmio.Mmio(packed struct(u32) {
/// EP_ID
EP_ID: u4 = 0x0,
/// DIR
DIR: u1 = 0x0,
reserved7: u2 = 0,
/// L1REQ
L1REQ: u1 = 0x0,
/// ESOF
ESOF: u1 = 0x0,
/// SOF
SOF: u1 = 0x0,
/// RESET
RESET: u1 = 0x0,
/// SUSP
SUSP: u1 = 0x0,
/// WKUP
WKUP: u1 = 0x0,
/// ERR
ERR: u1 = 0x0,
/// PMAOVR
PMAOVR: u1 = 0x0,
/// CTR
CTR: u1 = 0x0,
padding: u16 = 0,
}),
/// USB frame number register
/// offset: 0x48
FNR: mmio.Mmio(packed struct(u32) {
/// FN
FN: u11 = 0x0,
/// LSOF
LSOF: u2 = 0x0,
/// LCK
LCK: u1 = 0x0,
/// RXDM
RXDM: u1 = 0x0,
/// RXDP
RXDP: u1 = 0x0,
padding: u16 = 0,
}),
/// USB device address
/// offset: 0x4c
DADDR: mmio.Mmio(packed struct(u32) {
/// ADD
ADD: u7 = 0x0,
/// EF
EF: u1 = 0x0,
padding: u24 = 0,
}),
/// Buffer table address
/// offset: 0x50
BTABLE: mmio.Mmio(packed struct(u32) {
reserved3: u3 = 0,
/// BTABLE
BTABLE: u13 = 0x0,
padding: u16 = 0,
}),
};

29
src/stm32g4/types/peripherals/VREFBUF.zig Normal file
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@@ -0,0 +1,29 @@
const microzig = @import("microzig");
const mmio = microzig.mmio;
const types = @import("../../types.zig");
/// Voltage reference buffer
pub const VREFBUF = extern struct {
/// VREF_BUF Control and Status Register
/// offset: 0x00
VREFBUF_CSR: mmio.Mmio(packed struct(u32) {
/// Enable Voltage Reference
ENVR: u1 = 0x0,
/// High impedence mode for the VREF_BUF
HIZ: u1 = 0x1,
reserved3: u1 = 0,
/// Voltage reference buffer ready
VRR: u1 = 0x0,
/// Voltage reference scale
VRS: u2 = 0x0,
padding: u26 = 0,
}),
/// VREF_BUF Calibration Control Register
/// offset: 0x04
VREFBUF_CCR: mmio.Mmio(packed struct(u32) {
/// Trimming code
TRIM: u6 = 0x0,
padding: u26 = 0,
}),
};

37
src/stm32g4/types/peripherals/WWDG.zig Normal file
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const microzig = @import("microzig");
const mmio = microzig.mmio;
const types = @import("../../types.zig");
/// System window watchdog
pub const WWDG = extern struct {
/// Control register
/// offset: 0x00
CR: mmio.Mmio(packed struct(u32) {
/// 7-bit counter (MSB to LSB)
T: u7 = 0x7F,
/// Activation bit
WDGA: u1 = 0x0,
padding: u24 = 0,
}),
/// Configuration register
/// offset: 0x04
CFR: mmio.Mmio(packed struct(u32) {
/// 7-bit window value
W: u7 = 0x7F,
reserved9: u2 = 0,
/// Early wakeup interrupt
EWI: u1 = 0x0,
reserved11: u1 = 0,
/// Timer base
WDGTB: u3 = 0x0,
padding: u18 = 0,
}),
/// Status register
/// offset: 0x08
SR: mmio.Mmio(packed struct(u32) {
/// Early wakeup interrupt flag
EWIF: u1 = 0x0,
padding: u31 = 0,
}),
};

58
stm32g431cbtx.ld Normal file
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@@ -0,0 +1,58 @@
FLASH_SIZE = 0x1b580; /* 112k flash */
SRAM_SIZE = 0x8000; /* 32k sram */
STACK_SIZE = 0x400; /* 1k stack */
ENTRY(resetHandler)
MEMORY
{
sram (rwx) : ORIGIN = 0x20000000, LENGTH = SRAM_SIZE
flash (rx) : ORIGIN = 0x08000000, LENGTH = FLASH_SIZE
}
SECTIONS
{
.text :
{
. = ALIGN(4);
LONG(__initial_stack_pointer)
KEEP(*(.vectors))
*(.text*)
*(.rodata*)
. = ALIGN(4);
} > flash
.stack (NOLOAD) :
{
. = ALIGN(8);
. = . + STACK_SIZE;
. = ALIGN(8);
__initial_stack_pointer = .;
} > sram
.data :
{
_sdata = .;
. = ALIGN(4);
*(.data*)
. = ALIGN(4);
_edata = .;
} > sram AT> flash
_ldata = LOADADDR(.data);
.bss (NOLOAD) :
{
_szero = .;
. = ALIGN(4);
*(.bss*)
. = ALIGN(4);
_ezero = .;
} > sram
}

1281
temp.txt Normal file
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