added netclass colours

This commit is contained in:
sirlilpanda
2025-08-19 14:56:23 +12:00
parent 3794d90a5b
commit 4faf18c8e6

View File

@@ -472,6 +472,34 @@
"via_diameter": 0.6,
"via_drill": 0.3,
"wire_width": 6
},
{
"line_style": 0,
"name": "GND",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 1,
"schematic_color": "rgb(132, 132, 132)"
},
{
"line_style": 0,
"name": "HIGH_FREQ",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 0,
"schematic_color": "rgb(255, 255, 0)"
},
{
"line_style": 0,
"name": "POWER+",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 3,
"schematic_color": "rgb(255, 0, 0)"
},
{
"line_style": 0,
"name": "POWER-",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"priority": 2,
"schematic_color": "rgb(0, 0, 194)"
}
],
"meta": {
@@ -479,7 +507,32 @@
},
"net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
"netclass_patterns": [
{
"netclass": "POWER+",
"pattern": "^\\+[V|.|v]*.+[V|v]*"
},
{
"netclass": "POWER-",
"pattern": "^\\-[V|.|v]*.+[V|v]*"
},
{
"netclass": "HIGH_FREQ",
"pattern": "*HS"
},
{
"netclass": "GND",
"pattern": "*GND*"
},
{
"netclass": "POWER+",
"pattern": "*VCC"
},
{
"netclass": "POWER-",
"pattern": "*VS*"
}
]
},
"pcbnew": {
"last_paths": {